🚀 go-pugleaf

This goes out to anyone who has used HDL for digital design. I am
trying to build the structural model of a hypothetical instruction set
processor (ISP). 

Now my question is; When one is into structural modelling, & one
describes a component for example an AND gate. One describes the inputs,
the output, and the initial delay, rise time & fall time. These values
of tr, tf are very important. I am led to believe that if one uses 0ns
delay then we still end up with unit delays for each time the module is
used in a higher level. What do commercial designers use for these
values of tr & tf. 

In the industry if you are doing a structural model of some device &
your device uses about lets say '50 gates'(Example). What would be the
delays one would specify for the gates. What is it based upon

For example the project that I'm working on has about 20 odd registers,
2 source buses, 1 destination bus, an ALU , and an Address bus in the
Datapath. It also has a control unit, which gives the necessary control
signals to work the Datapath. Now since the entire processor is being
built hierarchically using lower level modules, what should I base my
delays on in the lower level models. Also how do I consider Bus delays.

I hope someone out there can really provide an answer to my question.
This is with regards to my M.S. thesis & I really need some advice on
this matter. If someone is willing to help , please reply by email & I
will explain my question again if necessary.

Thanks in advance,

-Deepak Kakadasam                             deepak@konark.njit.edu


--
VLSI:=> "Getting High On Low Voltage"       ** 
E15WNJTPXE15x280WXR1TL21NXL4TL17NXR10TL->    **    Those who can, DO
You can tune a guitar, but you cant tuna fish.**    Those who cant, TEACH.
*******************************************************************************