🚀 go-pugleaf

I feel your question is : how does the delays get `WORSE' after the
modules are interconnected...

When I tried it , I did the following.  In my verilog model I calculated
(By intuitive reasoning, thats the best students can do), the fan out of
each gate in the circuit.  90 % of the gates have fanout less than 2, especially
for me.  Unless you have a bus-oriented circuit.

Well, I then defined units for the fanout.  Using MAGIC, I approximated that
a fanout-load going into a three-input AND gate was like two NOT_gate_fanout.  etc...
All gates were `labelled' in NOT-gate-fanout-units.  Then for each
simple atomic unit, I simulated the performance for different # of NOT gates..

eg: I simulated IN MAGIC, the dalays when a two input AND gate drives 1, 2 , 4, 6 & 8
and 16 NOT gates.  Similarly, for NOT gates themselves, and OR / XOR, etc...

use the MAGIC results in verilog as the delay parameters.

This was the only solution for me.  I couldnt get hold of accurate
`foundry-data' -- that was impossible for me.  All we had a basic verilog simulator
and Public-Domain MAGIC...


Seetamraju Udaya Bhaskar Sarma
(email : seetam @ ece7 . eng . wayne . edu)