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Article View: comp.lang.verilog
Article #138

Memory Addressing in verilog

#138
From: Steve Wood
Date: Wed, 18 Nov 1992 18:19
20 lines
1437 bytes
I am trying to write a behavioural model for a family of modular 1- and
2-port memories and am new to the verilog language.  

I have been experimenting with "writing" (i.e. procedural assignment to
a memory register array) to the memory array with array index (address) set to "X".
Such a condition is a serious error in a real memory, however verilog seems
to ignore any out of range or unknown index when it is part of the LHS of a
procedural assignment.

My question is: does verilog do any bounds checking on index values to register
                arrays or do I have to implement such checks myself?
-- 
regards,

============================================================================================
Steven Wood			Phone: 613-763-2830
Memory Development		ESN:     6-393-2830
Bell Northern Research          Email: swood@bnr.ca (internet)
============================================================================================
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Message-ID: <1992Nov18.181933.10242@bcrka451.bnr.ca>
Path: arc1-ca.pugleaf.net!sparky!uunet!utcsri!skule.ecf!torn!nott!bnrgate!bcrka451!swood

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Newsgroups: comp.lang.verilog
Path: arc1-ca.pugleaf.net!sparky!uunet!utcsri!skule.ecf!torn!nott!bnrgate!bcrka451!swood
From: swood@bnr.ca (Steve Wood)
Subject:  Memory Addressing in verilog
Message-ID: <1992Nov18.181933.10242@bcrka451.bnr.ca>
Originator: swood@bcrks50
Keywords:  address, register array, bounds check
Sender: 5E00 Corkstown News Server
Reply-To: swood@bnr.ca (Steve Wood)
Organization: Bell-Northern Research, Ltd
Date: Wed, 18 Nov 1992 18:19:33 GMT
Lines: 21