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Article View: comp.lang.verilog
Article #139

Re: Avoiding inertial delay in delay lines

#139
From: Cindy Eisner
Date: Wed, 18 Nov 1992 06:16
38 lines
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In article <1992Nov16.163807.15366@dsg.tandem.com>, leung@DSG.Tandem.COM (Steven Leung) writes:
> 
> 
> BTW, putting the delay after the assignment operator appears to have
> some effects on scheduling. Even "a = #10 b;" has some difference from
> "#10 a = b;". (Don't know whether this is considered as a bug though.)
> 

look in the manual.  "a = #10 b;" means sample b NOW, and assign its value to
a in 10 time units.  on the other hand, "#10 a = b;" means wait 10 time units
starting from now, and then sample b and immediately assign the sampled value
to a.  

parts of this discussion seem to have passed my news feed by, but from what
i gather, using "a <= #10 b;" (non-blocking) should work for the original 
poster, since it will schedule the current value of b to be assigned in another
10 time units.  in the meantime, if b changes, before the 10 time units is up,
say at time 3, verilog will be free the execute the assignment again, and 
schedule another assignment at time 3+10=13.  

notice:  1.  you must use a non-blocking assignment, with the delay after
             the equals

         2.  you must make sure that the current always statement does not
             contain (other) blocking assignments which will mess up the
             scheduling of this assignment.  

hope this helps.

cindy.

-- 

    Cindy Eisner,                     Tel: 972-4-551551
    CAD group,                        Fax: 972-4-551550
    Zoran Microelectronics LTD,       E-mail: cindy@Zoran.HellNet.Org
    Advanced Technology Center
    Haifa 31204, Israel               Could be my employer doesn't agree.
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References: <1992Nov12.053306.12799@afterlife.ncsc.mil> <1992Nov12.142615.10697@m.cs.uiuc.edu> <1992Nov12.163116.17205@dsg.tandem.com> <1992Nov16.045205.22453@afterlife.ncsc.mil> <1992Nov16.163807.15366@dsg.tandem.com>

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Path: arc1-ca.pugleaf.net!sparky!uunet!imp!ca41!cindy
From: cindy@zoran.hellnet.org (Cindy Eisner)
Newsgroups: comp.lang.verilog
Subject: Re: Avoiding inertial delay in delay lines
Message-ID: <248@ca41.zoran.hellnet.org>
Date: 18 Nov 92 06:16:17 GMT
References: <1992Nov12.053306.12799@afterlife.ncsc.mil> <1992Nov12.142615.10697@m.cs.uiuc.edu> <1992Nov12.163116.17205@dsg.tandem.com> <1992Nov16.045205.22453@afterlife.ncsc.mil> <1992Nov16.163807.15366@dsg.tandem.com>
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