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Article View: comp.lang.verilog
Article #130

Re: Avoiding inertial delay in delay lines

#130
From: Steven Leung
Date: Mon, 16 Nov 1992 16:38
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smb@afterlife.ncsc.mil (Steve M. Burinsky) writes:

|> In article <1992Nov12.163116.17205@dsg.tandem.com> leung@DSG.Tandem.COM (Steven Leung) 
>
|> >	a <= #10 b;	/* transport delay */
|> >
|> 
|> I cannot see why a non-blocking assignment should operate any differently
|> than a blocking assignment in terms of how events are scheduled.  Thus,
|> I expected that the above would not work.  However, it does, as does
|> 
|> 	#10 a <= b;

Are you sure? I check my experiments again and pretty sure that putting
the delay in front of the assignment statement will not make the delay
become transport. It behaves exactly the same as #10 a = b;.

BTW, putting the delay after the assignment operator appears to have
some effects on scheduling. Even "a = #10 b;" has some difference from
"#10 a = b;". (Don't know whether this is considered as a bug though.)

Steven
-- 
328. Seek opportunity, not security. ...
        - Life's Little Instruction Book by H. J. Brown, Jr.
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Message-ID: <1992Nov16.163807.15366@dsg.tandem.com>
Path: arc1-ca.pugleaf.net!sparky!uunet!think.com!ames!pacbell.com!tandem!dsg.tandem.com!leung
References: <1992Nov12.053306.12799@afterlife.ncsc.mil> <1992Nov12.142615.10697@m.cs.uiuc.edu> <1992Nov12.163116.17205@dsg.tandem.com> <1992Nov16.045205.22453@afterlife.ncsc.mil>

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Path: arc1-ca.pugleaf.net!sparky!uunet!think.com!ames!pacbell.com!tandem!dsg.tandem.com!leung
From: leung@DSG.Tandem.COM (Steven Leung)
Subject: Re: Avoiding inertial delay in delay lines
Message-ID: <1992Nov16.163807.15366@dsg.tandem.com>
Originator: leung@bittemple
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Organization: Tandem Computers
References: <1992Nov12.053306.12799@afterlife.ncsc.mil> <1992Nov12.142615.10697@m.cs.uiuc.edu> <1992Nov12.163116.17205@dsg.tandem.com> <1992Nov16.045205.22453@afterlife.ncsc.mil>
Date: Mon, 16 Nov 1992 16:38:07 GMT
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