Article View: comp.lang.verilog
Article #122Re: Verilog <--> VHDL translators
From: Masaharu Goto
Date: Mon, 21 Dec 1992 18:07
Date: Mon, 21 Dec 1992 18:07
45 lines
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2503 bytes
I posted the same question a couple of months ago and got some information. I am very interested in the same issue. I would appreciate if you would share me the information you would get too. So far, what I get to know are Commercial availability of the Verilog <-> VHDL translators Cadence VDOC-454 Verilog to VHDL translator Cadence is the originator of the Verilog-HDL and it seems like VDOC-454 has a quite good coverage on Verilog to VHDL translation. It costs $200k~300k. It translates User Defined Primitives and architectural description very good. Now, I am giving my benchmark example to see how good it translates behavioral Verilog description to VHDL. I will let you know when their benchmark comes out. I am not sure if they have VHDL to Verilog translator. InterHDL Verilog <-> VHDL translator A company called InterHDL has Verilog to VHDL and VHDL to Verilog translator. I don't have any further information about their products now. Synopsys If the Verilog or VHDL description is logic synthesizable (means written in Register Transfer Level), Synopsys can do the job too. It means it can only translate subset of the language. I didn't get any information about public domain Verilog <-> VHDL translator so far. I imagine there are no such things because there are very few people in this planet who has an access to both Verilog and VHDL based simulator at this moment. My own observation and comment about the issue is, language definition of the Verilog-HDL is closely related to implementation of the Verilog-XL simulator. And some of its' features are not essential to describe Hardware but essential to speed up simulation throughput. On the other hand, VHDL is more pure for describing Hardware. I think somebody needs to work out to accumurate those differences to make a good translator. I am not sure if this is very realistic but it would be very nice that somebody in the world defines subset of those language for portability of the HDL description.
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From: gotom@hpysoln.tky.hp.com (Masaharu Goto) Date: Mon, 21 Dec 1992 18:07:02 GMT Subject: Re: Verilog <--> VHDL translators Message-ID: <32560002@hpysoln.tky.hp.com> Organization: YHP Hachioji IT, Tokyo Japan Path: arc1-ca.pugleaf.net!sparky!uunet!zaphod.mps.ohio-state.edu!sdd.hp.com!hpscit.sc.hp.com!hplextra!hpcc05!hpyhde4!hpysoln!gotom Newsgroups: comp.lang.verilog References: <d+V=MG#@engin.umich.edu> Lines: 46