🚀 go-pugleaf

In using the verilog language I've noticed the language
will allow you to do many things you don't necessarily
want to do.  Like the C language it is very flexible, 
unfortunately unlike C there isn't a program verifier
like lint.  I can think of many things I'd like to be
checked, things that if checked would eliminate some
of the debugging phase. (My recent post on execution
of always blocks is one example, another is missing
event triggers for always blocks, or declared but 
unreferenced reg or wire variables, or ....)

Anybody heard of a tool like this?

dave
manley@optilink.com