Page 1 of 3 • 118 total threads
Discussion Threads in comp.lang.verilog
118 threads • Page 1 of 3| Thread Subject | Last Message |
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Premodded Video Games & Backups For Sale
By: milli on Thu, 11 Jun 2009 01:20 |
17 Years 5 Months ago
0 replies |
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__Cut and Paste C codes, you can have your hardware!
By: kctang on Mon, 12 Mar 2001 07:13 |
25 Years 8 Months ago
1 replies |
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JOB: USA-CA-San Jose: EDA Applications Engineer
By: Rich Newton on Wed, 28 Apr 1999 00:00 |
27 Years 6 Months ago
0 replies |
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Looking for ASIC layout contractor with Cadence tool experience
By: Michael T. Horne on Thu, 28 Aug 1997 00:00 |
29 Years 2 Months ago
0 replies |
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VERIFICATION ENGINEER OPENING
By: Daniel Chapiro on Mon, 06 Jan 1997 00:00 |
29 Years 10 Months ago
0 replies |
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SW Engineer: San Jose, C/C++, EDA, Flex/Bison, Verilog/VHDL
By: Rich Edelman on Fri, 25 Oct 1996 00:00 |
30 Years ago
0 replies |
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ANNOUNCE -- TRAINING: Intro/Advanced High Level Design Using HDLs, Bay Area
By: Qualis Training Registrar on Wed, 03 Apr 1996 00:00 |
30 Years 7 Months ago
0 replies |
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COURSES: Intro/Advanced High Level Design Using HDLs, Santa Clara, CA
By: Qualis Training Registrar on Mon, 18 Mar 1996 00:00 |
30 Years 8 Months ago
0 replies |
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COURSE: Advanced Techniques Using Verilog, March 18-20, Beaverton OR
By: Qualis Training Registrar on Tue, 27 Feb 1996 00:00 |
30 Years 8 Months ago
0 replies |
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COURSE: High Level Design Using VHDL, March 11-15, Beaverton OR
By: Qualis Training Registrar on Tue, 27 Feb 1996 00:00 |
30 Years 8 Months ago
0 replies |
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COURSE: High Level Design Using Verilog, March 25-29, Beaverton OR
By: Qualis Training Registrar on Tue, 27 Feb 1996 00:00 |
30 Years 8 Months ago
0 replies |
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COURSE: High Level Design Using VHDL, March 11-15, Beaverton OR
By: Qualis Registrar on Wed, 31 Jan 1996 00:00 |
30 Years 9 Months ago
0 replies |
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COURSE: High Level Design Using Verilog, Feb 12-16, Beaverton OR
By: Training Registrar on Wed, 31 Jan 1996 00:00 |
30 Years 9 Months ago
0 replies |
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COURSE: Advanced Techniques Using Verilog, March 4-6, Beaverton OR
By: Training Registrar on Wed, 31 Jan 1996 00:00 |
30 Years 9 Months ago
0 replies |
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Wanted talented design/verification engineers for the Indus family.
By: Samir Palnitkar on Tue, 02 Jan 1996 00:00 |
30 Years 10 Months ago
0 replies |
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COURSE: High Level Design Using VHDL, Feb, Beaverton OR
By: Qualis Training Registrar on Fri, 01 Dec 1995 00:00 |
30 Years 11 Months ago
0 replies |
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COURSE: High Level Design Using Verilog, Dec, Jan, Feb, Beaverton OR
By: Qualis Training Registrar on Fri, 01 Dec 1995 00:00 |
30 Years 11 Months ago
0 replies |
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COURSE: High Level Design Using Verilog, Dec, Jan, Feb, Beaverton OR
By: Qualis Training Registrar on Thu, 23 Nov 1995 00:00 |
30 Years 11 Months ago
0 replies |
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COURSE: High Level Design Using VHDL, Dec, Feb, Beaverton OR
By: Qualis Training Registrar on Thu, 23 Nov 1995 00:00 |
30 Years 11 Months ago
0 replies |
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COURSE: High Level Design Using Verilog, Nov 6-10, Beaverton OR
By: training on Fri, 06 Oct 1995 00:00 |
31 Years 1 Month ago
0 replies |
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COURSE: High Level Design Using VHDL, Oct 30-Nov 3, Beaverton OR
By: training on Fri, 06 Oct 1995 00:00 |
31 Years 1 Month ago
0 replies |
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COURSE: High Level Design Using VHDL, Oct 2-6, Beaverton OR
By: training on Fri, 15 Sep 1995 00:00 |
31 Years 2 Months ago
0 replies |
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COURSE: High Level Design Using Verilog, Oct 9-13, Beaverton OR
By: training on Fri, 15 Sep 1995 00:00 |
31 Years 2 Months ago
0 replies |
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Qualis Top-Down Design With Verilog Course: July 17-21
By: Clifford E. Cummings on Thu, 15 Jun 1995 00:00 |
31 Years 5 Months ago
0 replies |
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Job Opening - Corporate Applications Engineer
By: Viewlogic Systems, Inc. on Thu, 09 Feb 1995 15:38 |
31 Years 9 Months ago
0 replies |
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Verilog books
By: Andrew Guillaume on Fri, 29 Jan 1993 04:53 |
33 Years 9 Months ago
0 replies |
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Best possible Verilog Reference: Also software Harddware co-design
By: Tapas Shome on Wed, 27 Jan 1993 06:22 |
33 Years 9 Months ago
0 replies |
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Books on Verilog
By: Jim Hunt on Wed, 27 Jan 1993 03:49 |
33 Years 9 Months ago
0 replies |
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Int'l Conference on CAD, ICCAD93 (CFP: papers due 4/12/93)
By: Gaetano Borriello on Tue, 26 Jan 1993 17:04 |
33 Years 9 Months ago
0 replies |
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Free Xilinx Simulation Interface for Verilog
By: Daniel R. Kegel on Fri, 22 Jan 1993 18:48 |
33 Years 9 Months ago
0 replies |
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Verilog code for Inverted, Open collector, Output Enable Bus
By: Tai Phan on Thu, 21 Jan 1993 16:17 |
33 Years 9 Months ago
1 replies |
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Request for information on a verilog mode for GNU Emacs
By: Roy Tobin on Thu, 21 Jan 1993 18:13 |
33 Years 9 Months ago
0 replies |
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Joining ESNUG
By: John Cooley on Thu, 21 Jan 1993 05:44 |
33 Years 9 Months ago
0 replies |
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Re: Verilog <--> VHDL translators
By: John Cooley on Tue, 05 Jan 1993 05:46 |
33 Years 10 Months ago
1 replies |
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Verilog <--> VHDL translators
By: Tony Pham on Fri, 18 Dec 1992 02:46 |
33 Years 10 Months ago
3 replies |
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New question - lint like verilog checker
By: Terry Manley on Tue, 22 Dec 1992 00:17 |
33 Years 10 Months ago
2 replies |
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Re: Verilog Syntax/Semantics Checker
By: Dan Sharoni on Tue, 22 Dec 1992 17:37 |
33 Years 10 Months ago
0 replies |
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execution of always blocks
By: Terry Manley on Thu, 17 Dec 1992 07:15 |
33 Years 10 Months ago
5 replies |
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Conversion of Verilog timing checks to VHDL?
By: Daniel R. Kegel on Fri, 18 Dec 1992 04:36 |
33 Years 11 Months ago
0 replies |
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Ignore this dumb test message!
By: gordjericho.uucp Gord Wait on Tue, 15 Dec 1992 18:55 |
33 Years 11 Months ago
0 replies |
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Re: verilog and synthesis
By: John Cooley on Sun, 13 Dec 1992 04:08 |
33 Years 11 Months ago
0 replies |
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HELP:Verilog to VHDL translator
By: Masaharu Goto on Thu, 19 Nov 1992 16:34 |
33 Years 11 Months ago
1 replies |
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Does OVI read mail?
By: Richard D. Schlotfeldt on Mon, 23 Nov 1992 22:37 |
33 Years 11 Months ago
0 replies |
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2nd Annual Int'l Verilog HDL Conference - March 22-24
By: OVI on Mon, 23 Nov 1992 19:31 |
33 Years 11 Months ago
0 replies |
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Verilog LSI/MSI libs?
By: Manolis Stratakis on Fri, 20 Nov 1992 10:40 |
33 Years 12 Months ago
0 replies |
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3rd Party Verilog Compilers
By: Bruce Dunlop on Thu, 12 Nov 1992 21:11 |
33 Years 12 Months ago
4 replies |
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Info about OVI and status of Verilog
By: Clint Olsen on Fri, 20 Nov 1992 00:22 |
33 Years 12 Months ago
0 replies |
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Memory Addressing in verilog
By: Steve Wood on Wed, 18 Nov 1992 18:19 |
33 Years 12 Months ago
1 replies |
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Invite to Join ESNUG
By: John Cooley on Wed, 18 Nov 1992 09:20 |
33 Years 12 Months ago
0 replies |
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Avoiding inertial delay in delay lines
By: Steve M. Burinsky on Thu, 12 Nov 1992 05:33 |
33 Years 12 Months ago
6 replies |
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