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In article <13665@optilink.COM> manley@optilink.COM (Terry Manley) writes:

   Ok, I've got a 'newbie' question.

   What's the story with this language?

Since I just took a class on Verilog, I'll try to answer your question.
It's a good test to see if I learned anything :) I am sure I will be
corrected if I am wrong.

   More specifically why doesn't the following work:

   reg a,b,c;

   always @(posedge Clk) c = b;
   always @(posedge Clk) b = a;

The assignments occur on the posedge of the Clk, but there is nothing in
this structure that says which should occur first. In theory they should
occur at the same time, but this setup does not guarantee this. If you
want that you should use the fork ... join construct.

   When the following does:

   always @(posedge Clk)
     begin
	   c = b;
	   b = a;
     end

In this case, the action will start on the posedge of Clk. Then, because
you used a begin ... end block, versus the fork ... join, the assignments
will take place sequentially. 

	c gets the value of b
	b gets the value of a

This all takes place in zero time. To have these occur in parallel, you
could use:

	always @(posedge Clk)
	  fork
		c = b;
		b = a;
	  join

However, this has the same problem as the two always blocks, there is no
control over which will take place first. I can't remember the exact syntax,
but there is a way to specify that the values of b & a are first saved and
then the assignments take place. This allows them to occur in any order, but
get the results you are after.

   In the first case for some reason verilog may perform the "b = a"
   assignment first, thereby throwing away the expected value that c was
   going to get.  We've even seen cases where in a given simulation
   sometimes it works correctly, sometimes it doesn't.

   Ideally one would want the data transfer at the posedge of the clock
   to behave like digital logic, that is it would, in this case behave
   like a shift register.  Instead we get what looks like a shift
   register with a bad hold time problem. 

   So what is the story with multiple always blocks?
   Is this something to worry about between modules?
   How about between modules in different files?

If the actions occur within separate modules, you need to have event controls
to ensure the actions take place in the order you want if that matters.


   --
   dave
   manley@optilink.com

--
Alan Bair             		AMCU DSCS
Motorola, Inc.            	    (Design Software &
Mail Stop OE-320		     Computer Services)
6501 William Cannon Dr. West	
Austin, TX  78735-8598          abair@parsons.sps.mot.com

manley@optilink.COM (Terry Manley) writes:

> always @(posedge Clk) c = b;
> always @(posedge Clk) b = a;

Verilog does not guarantee the sequence of execution of
multiple procedural blocks such as the always blocks above.
If you have to use two always blocks, you could put
a #0 delay before the procedural assignment that you want
done last. That will make VerilogXL schedule that event
for processing at the end of that timestamp.

---
Rajesh Patil
----------------------------------------------------------------------
Advanced Product Operations                 rajesh@chdasic.sps.mot.com
Motorola ASIC                               
----------------------------------------------------------------------

In article <1992Dec18.174451.11544@newsgate.sps.mot.com> rajesh@chdasic.sps.mot.com writes:
>manley@optilink.COM (Terry Manley) writes:
>
>> always @(posedge Clk) c = b;
>> always @(posedge Clk) b = a;
>
>If you have to use two always blocks, you could put
>a #0 delay before the procedural assignment that you want
>done last. That will make VerilogXL schedule that event
>for processing at the end of that timestamp.

Which is fine if you only care about which ONE is last.  If you have 
three (or more) registers, you'll still have problems.  Using the
non-blocking assignment operator ( <= ) will give you the behavior you want:

 always @(posedge Clk) c <= b;
 always @(posedge Clk) b <= a;

In article <1992Dec18.200153.25828@twisto.eng.hou.compaq.com> ehlers@tiktok.eng.hou.compaq.com (Steve Ehlers) writes:
>In article <1992Dec18.174451.11544@newsgate.sps.mot.com> rajesh@chdasic.sps.mot.com writes:
>>manley@optilink.COM (Terry Manley) writes:
>>
>>> always @(posedge Clk) c = b;
>>> always @(posedge Clk) b = a;
>>
>>If you have to use two always blocks, you could put
>>a #0 delay before the procedural assignment that you want
>>done last. That will make VerilogXL schedule that event
>>for processing at the end of that timestamp.
>
>Which is fine if you only care about which ONE is last.  If you have 
>three (or more) registers, you'll still have problems.  Using the
>non-blocking assignment operator ( <= ) will give you the behavior you want:
>
> always @(posedge Clk) c <= b;
> always @(posedge Clk) b <= a;

Intra-assignment timing provides another alternative
(The following example can be run as is).

/* Example of "intra-assignment" timing control across */
/* procedural blocks. Placing timing control on the    */
/* right-hand side (RHS) of the "=" causes temporary   */
/* storage of the RHS variable, and schedules future   */
/* assignment using the stored RHS value.              */
/*                                                     */
/* Cliff Cummings - 12/18/92                           */

`timescale 1ns /100ps
module Qintra;
  reg [3:0] a, b;
  reg clk;

  // Wait 1 time unit to allow initial assignment of "b"
  always #1 a = @(posedge clk) b;

  // Wait 1 time unit to allow initial assignment of "a"
  always #1 b = @(posedge clk) a;

  initial begin
      clk = 0;
      forever #10 clk = ~clk;
    end

  initial begin
      $timeformat(-9, 2, "ns", 10);
      #1 $monitor($time, ": a = %h,  b = %h", a, b);
    end

  initial begin
      a=4'h5; b=4'ha;
      #100 $stop;
      #100 $finish;
    end
      
endmodule

In article <1992Dec18.200153.25828@twisto.eng.hou.compaq.com> ehlers@tiktok.eng.hou.compaq.com (Steve Ehlers) writes:
>Which is fine if you only care about which ONE is last.  If you have 
>three (or more) registers, you'll still have problems.  Using the
>non-blocking assignment operator ( <= ) will give you the behavior you want:
>
> always @(posedge Clk) c <= b;
> always @(posedge Clk) b <= a;

I've always wondered why Verilog, an HDL, had a blocking assignment as
the default to begin with. Early Verilog designs were excessively verbose,
with the creation of non-existant "registers" and wire delay terms to
get around this problem. The recent introduction of the non-blocking
assignemnt seems to me long overdue on the part of the language designers.

With the non-blocking assignemnt, what used to be somewhat tedious is now
a breeze as the model works exactly like I expect the hardware to.

-- 
Michael Lodman	Department of Computer Science Engineering
	University of California, San Diego
jlodman@cs.ucsd.edu		      (619) 455-1500 x2627