🚀 go-pugleaf

In article <1992Dec18.200153.25828@twisto.eng.hou.compaq.com> ehlers@tiktok.eng.hou.compaq.com (Steve Ehlers) writes:
>Which is fine if you only care about which ONE is last.  If you have 
>three (or more) registers, you'll still have problems.  Using the
>non-blocking assignment operator ( <= ) will give you the behavior you want:
>
> always @(posedge Clk) c <= b;
> always @(posedge Clk) b <= a;

I've always wondered why Verilog, an HDL, had a blocking assignment as
the default to begin with. Early Verilog designs were excessively verbose,
with the creation of non-existant "registers" and wire delay terms to
get around this problem. The recent introduction of the non-blocking
assignemnt seems to me long overdue on the part of the language designers.

With the non-blocking assignemnt, what used to be somewhat tedious is now
a breeze as the model works exactly like I expect the hardware to.

-- 
Michael Lodman	Department of Computer Science Engineering
	University of California, San Diego
jlodman@cs.ucsd.edu		      (619) 455-1500 x2627