New question - lint like verilog checker - Thread - go-pugleaf

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3 total messages Started by Terry Manley Tue, 22 Dec 1992 00:17

New question - lint like verilog checker

#121

Author: Terry Manley
Date: Tue, 22 Dec 1992 00:17

15 lines
886 bytes

In using the verilog language I've noticed the language
will allow you to do many things you don't necessarily
want to do.  Like the C language it is very flexible, 
unfortunately unlike C there isn't a program verifier
like lint.  I can think of many things I'd like to be
checked, things that if checked would eliminate some
of the debugging phase. (My recent post on execution
of always blocks is one example, another is missing
event triggers for always blocks, or declared but 
unreferenced reg or wire variables, or ....)

Anybody heard of a tool like this?

dave
manley@optilink.com

Re: New question - lint like verilog checker

#123

Author: Jeff West
Date: Tue, 22 Dec 1992 15:53

26 lines
1328 bytes

manley@optilink.COM (Terry Manley) writes:
: In using the verilog language I've noticed the language
: will allow you to do many things you don't necessarily
: want to do.  Like the C language it is very flexible, 
: unfortunately unlike C there isn't a program verifier
: like lint.  I can think of many things I'd like to be
: checked, things that if checked would eliminate some
: of the debugging phase. (My recent post on execution
: of always blocks is one example, another is missing
: event triggers for always blocks, or declared but 
: unreferenced reg or wire variables, or ....)
: 
: Anybody heard of a tool like this?
: 
: dave
: manley@optilink.com

There is a tool called Verilint from the Veritools company.  I have
no experience with it though.

Jeff

---------------------------------------------------------------------
It's not denial.  I'm just very selective about the reality I accept.

    - Calvin & Hobbs

Re: New question - lint like verilog checker

#125

Author: Interpretive Systems
Date: Tue, 22 Dec 1992 22:40

12 lines
901 bytes

InterHDL has a program which does what you just wanted. Verilint is a
lint program (syntax/semantics checker) for Verilog. It is available for
beta sites on PC, HP and Sun workstations. For more info send mail directly to me.

Eli Sternheim
interHDL Design Corp.
1270 Oakmead Pkwy #209
Sunnyvale, CA 94086
(408) 749-8775
FAX (408) 749-8823
eli@netcom.com

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