🚀 go-pugleaf

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First off, apologies in advance to those who don't think job postings belong 
on the comp.lang.* newsgroups. A recent thread on comp.lang.verilog included 
opinions on both sides. Flame away if it makes you feel better.
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Chrysalis Symbolic Design has openings for Applications Engineers for our 
Campbell, CA office! Join the rapidly growing, pre-IPO market leader in a 
hot area of EDA!

For more information about Chrysalis and its products, see www.chrysalis.com

This position is focused on introducing to the complex IC or ASICS design 
community to formal verification. This includes both equivalency checking 
and model checking. The Application Engineering role is a dynamic job, 
involving working closely with customers as well as most areas within
Chrysalis (i.e. sales, marketing, engineering, etc.)

It requires direct interaction with customers in both pre and postsales 
environments supporting technical evaluations and benchmarks, demos and 
technical presentations. This role leverages your IC or ASIC design 
background to introduce and support customers with formal verification 
software, and gives you the opportunity to identify new products, 
applications, improvements, and business opportunities for this technology. 
Some travel is required.

Position requires 3 or more years design experience of complex or ASIC or 
ICs or EDA AE experience. Excellent problem solving and communication skills 
required. BSEE/BSCS or MSEE preferred. Design language experience (VHDL or 
Verilog) and design or application engineering experience required.

To avoid deluging our HR person with spam, I'm not going to post her email 
here - please visit the Chrysalis web site career section at 
http://www.chrysalis.com/careers.html for information on how to apply.

Thanks!