🚀 go-pugleaf

Qualis Design Corporation will be offering another session of its popular
course, `A Comprehensive Introduction to High Level Design Using VHDL' in
October.  Additional details are provided below.

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          A Comprehensive Introduction to High Level Design
                              Using VHDL

                         October 2 - 6, 1995
                          Beaverton, Oregon

                             Presented by
                      Qualis Design Corporation

`A Comprehensive Introduction to High Level Design Using VHDL' is a
fast paced, 5-day hands-on, multi-media course designed not only to
teach High Level Design techniques and the VHDL language, but to make
class participants immediately productive in a system design
environment using state-of-the-art simulation and synthesis tools.

After an introduction to VHDL, the course deviates from the
traditional bottom-up, gates-to-behavioral modeling presentation of
other VHDL courses and reverses the flow, teaching top-down design
practices, with early special emphasis on coding for synthesis,
efficient testbench generation and advanced design verification
techniques. These skills are reinforced throughout the week while
teaching VHDL from a top-down perspective.

The course labs accommodate the learning aptitudes of a wide range of
students with diverse design experiences. Each lab is structured into
three parts:

     1.        Fundamental Concepts Review and Experience
     2.        Recognition of Common Mistakes and Correcting Problems
     3.        Additional Material for Advanced Students

Parts one and two of each lab are completed by all students.  Part
three is for students who finish early and want to learn additional
material. This lab structure caters to all student skill levels and
provides excellent opportunities to expand one's knowledge of VHDL
simulation and synthesis techniques.

Each day of class includes interactive lecture sessions with 2 labs.
Students will have access to individual Sun Sparcstations, the
Synopsys VSS and Model Technology V-System/Workstation simulation
environments, and the Synopsys DC Expert synthesis environment for use
during the laboratory sessions. The instructor presents the material
using a projection system that allows 30% more material to be
presented in a given amount of time with vivid, interest-grabbing
color slides, as compared to black & white overheads.

About Your Instructor
---------------------
`A Comprehensive Introduction to High Level Design Using VHDL' is
conducted by Janick Bergeron, Director of Technology and Principal
Engineer at Qualis Design.  Mr. Bergeron has completed many ASIC
designs and system simulation projects, and is capable of answering
the very technical questions asked by experienced design engineers.

Mr. Bergeron has presented dozens of introductory, intermediate and
advanced workshops and tutorials on topics including top-down design,
test methodology, bus-functional modeling, logic synthesis, generation
of EDIF from VHDL and introduction to modeling using both VHDL and
Verilog.  One of Mr. Bergeron's works was voted Best Paper at the 1991
European VHDL Users Forum.  He was also a member of the technical
program committee for the 1995 Spring VHDL International Users Forum.
Mr. Bergeron is the author of the VHDL Makefile generator utility
`vmk'.

Mr. Bergeron holds a B.Eng from the Universite du Quebec a Chicoutimi
and an M.A.Sc. in EE from the University of Waterloo.  Mr. Bergeron is
a candidate for the degree of Master of Business Administration
through the Oregon Executive MBA program from the University of
Oregon.

About Qualis Design Corporation
-------------------------------
Founded in 1992, Qualis Design Corporation has quickly become the
leading independent provider of High Level Design consulting and
training services.  The company provides services to leading-edge high
technology firms worldwide, including Intel, Hewlett-Packard,
Tektronix, Xerox, TRW and Bell-Northern Research.

Qualis High Level Design Training Courses are conducted on leading-
edge Sun workstations using the latest EDA vendor tools, and are
taught by engineering professionals with extensive digital design
experience.  Engineers who complete the High Level Design With VHDL
course will be more efficient users of system simulation tools, will
be capable of implementing advanced simulation environments, and will
have the knowledge to successfully complete complex design projects.
Engineers with previous exposure to VHDL and Verilog will also benefit
from the leading-edge material presented.

Additional Information
----------------------
The High Level Design Using VHDL course is taught over five
consecutive days.  Complimentary continental breakfast, a full lunch
and afternoon refreshments are provided for each day of the class.
Lodging conveniently located near the class site is available, with
morning and evening shuttle service.

The next regularly scheduled class date is:

`A Comprehensive Introduction to High Level Design Using VHDL'

     Class Date:    October 2 - 6, 1995
     Time:          8:30 AM to 5:00 PM

     Class Location:
                    Qualis Design Corporation
                    15455 NW Greenbrier Parkway
                    Conference Room A/B
                    Beaverton, OR

For more information about this course, including course description
and syllabus, contact us at:

                      Qualis Design Corporation
                     15455 NW Greenbrier Parkway
                              Suite 250
                       Beaverton, OR 97006 USA

                        Phone: +1-503-531-0377
                         FAX: +1-503-629-5525
                     E-mail: training@qualis.com

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Copyright (c) 1995 Qualis Design Corporation.  All rights reserved.

`DC Expert' is a trademark of Synopsys, Inc.
`V-System/Workstation' is a trademark of Model Technology, Inc.
`Verilog' is a registered trademark of Cadence Design Systems, Inc.