Looking for ASIC layout contractor with Cadence tool experience

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1 total messages Started by Michael T. Horne Thu, 28 Aug 1997 00:00

#174

Author: Michael T. Horne
Date: Thu, 28 Aug 1997 00:00

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A close client of ours is looking for an expert in back-end layout of
large gate count (500K+ gate) CMOS standard cell ASICs, preferrably using
the Cadence toolset.  If you have experience and are available in the
near future, please send me e-mail at mikeh@qualis.com, or call me
at 503-644-9700.  If you're really hot, FAX your resume to me at
503-643-1583.

Since Qualis is not a placement agency nor a job shop, you will work
directly with our client (we will not be involved).  We are helping our
client find a much-needed resource simply as a favor to them.

Michael Horne
mikeh@qualis.com
http://www.qualis.com

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