Looking for ASIC layout contractor with Cadence tool experience

Article View: comp.lang.verilog

Article #174

#174

From: Michael T. Horne
Date: Thu, 28 Aug 1997 00:00

16 lines
1483 bytes


A close client of ours is looking for an expert in back-end layout of
large gate count (500K+ gate) CMOS standard cell ASICs, preferrably using
the Cadence toolset.  If you have experience and are available in the
near future, please send me e-mail at mikeh@qualis.com, or call me
at 503-644-9700.  If you're really hot, FAX your resume to me at
503-643-1583.

Since Qualis is not a placement agency nor a job shop, you will work
directly with our client (we will not be involved).  We are helping our
client find a much-needed resource simply as a favor to them.

Michael Horne
mikeh@qualis.com
http://www.qualis.com

Technical Details

Message-ID: <5u2h5l$bei$1@news.rain.net>

Path: arc1-ca.pugleaf.net!unknown!not-for-mail

Show Full Headers

Complete Article Headers

X-Google-Language: ENGLISH,ASCII-7-bit
X-Google-Thread: 111882,f210c64362577c2b,start
X-Google-Attributes: gid111882,public
X-Google-Thread: 10270d,f210c64362577c2b,start
X-Google-Attributes: gid10270d,public
X-Google-Thread: 102486,f210c64362577c2b,start
X-Google-Attributes: gid102486,public
X-Google-Thread: 112e4c,f210c64362577c2b,start
X-Google-Attributes: gid112e4c,public
X-Google-Thread: 1089ad,f210c64362577c2b,start
X-Google-Attributes: gid1089ad,public
From: mikeh@qualis.qualis.com (Michael T. Horne)
Subject: Looking for ASIC layout contractor with Cadence tool experience
Date: 1997/08/28
Message-ID: <5u2h5l$bei$1@news.rain.net>
X-Deja-AN: 268675587
Distribution: na
Organization: Qualis Design Corporation, Beaverton, OR
Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.cad.cadence,misc.jobs.contract,ba.jobs