Conversion of Verilog timing checks to VHDL?

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1 total messages Started by Daniel R. Kegel Fri, 18 Dec 1992 04:36

#153

Author: Daniel R. Kegel
Date: Fri, 18 Dec 1992 04:36

11 lines
764 bytes

Hi all,
is there an accepted idiom for expressing the sort of timing checks
supported in Verilog, i.e.
    $width(negedge x, t0);
    $setup(x, posedge y, t0);
    $hold(posedge x, y, t0);
in VHDL?

I'm thinking about converting a PD program that generates Verilog
to also generate VHDL.
- Dan Kegel (dank@blacks.jpl.nasa.gov)

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