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Conversion of Verilog timing checks to VHDL?
From: Daniel R. Kegel
Date: Fri, 18 Dec 1992 04:36
Article: 153
Message-ID: <dank.724653378@blacks.jpl.nasa.gov>
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- Subject: Conversion of Verilog timing checks to VHDL?
- From: Daniel R. Kegel
- Date: Fri, 18 Dec 1992 04:36
- Article: 153