Verilog code for Inverted, Open collector, Output Enable Bus

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2 total messages Started by Tai Phan Thu, 21 Jan 1993 16:17

#159

Author: Tai Phan
Date: Thu, 21 Jan 1993 16:17

35 lines
1395 bytes

Greetings,

If anyone knows a simple way to describe in Verilog an Open collector, Inverted,
with Output enable bus, please help.  The parameters are as follow:

// Verilog code

input [31:0] inp;               // Input bus
input oen_;                     // Output enable
output [31:0] outp_;            // Output bus

// When oen_ is 1, outp_ should be 32'hzzzzzzzz
// when oen_ is 0, outp_ is 0 if inp is 1, and z if inp is 0 (OC inverted)
// For single bit, I have the code that works:

wire [31:0] outp_;
assign outp_[31] = (~oen_ && inp[31]) ? 'b0 : 'bz;
assign outp_[30] = (~oen_ && inp[30]) ? 'b0 : 'bz;
.......
and so on
But this takes a lot of space, and typing. I want to use one or two lines
to describe the entire 32 bits bus.

Thanks,

Tai Phan
--------
Interphase Corp.
(214) 919 9000
phan@iphase.com


-- 
Tai Phan  X218
phan@iphase.com

Re: Verilog code for Inverted, Open collector, Output Enable Bus

#160

Author: Clifford E Cummings
Date: Thu, 21 Jan 1993 20:53

63 lines
2218 bytes

In article <C17p8K.7nA@iphase.com> phan@iphase.com (Tai Phan) writes:
>If anyone knows a simple way to describe in Verilog an Open collector, 
>Inverted, with Output enable bus, please help.  The parameters are as follow:
>
>// Verilog code
>
>input [31:0] inp;               // Input bus
>input oen_;                     // Output enable
>output [31:0] outp_;            // Output bus
>
>// When oen_ is 1, outp_ should be 32'hzzzzzzzz
>// when oen_ is 0, outp_ is 0 if inp is 1, and z if inp is 0 (OC inverted)
>// For single bit, I have the code that works:
>
>wire [31:0] outp_;
>assign outp_[31] = (~oen_ && inp[31]) ? 'b0 : 'bz;
>assign outp_[30] = (~oen_ && inp[30]) ? 'b0 : 'bz;
>.......
>and so on
>
>Thanks,
>
>Tai Phan
>--------
>Interphase Corp.
>(214) 919 9000
>phan@iphase.com

Is this what you are looking for? (this example can be run)

`timescale 1ns/100ps
module oc_bus( outp_, inp, oen_);
  // Verilog code
  input [31:0] inp;               // Input bus
  input oen_;                     // Output enable
  output [31:0] outp_;            // Output bus

  triand (strong1, highz0) [31:0] outp_ = (~oen_ ? ~inp : 32'bz);

endmodule

module oc_bus_test;
  reg  [31:0] inbus;
  reg         busen_;
  wire [31:0] outbus;

  oc_bus b1( outbus, inbus, busen_);

  initial
  $monitor("inbus = %h | busen_ = %h | outbus = %h \n",
      inbus, busen_, outbus,
      "                               (binary)= %b \n", 
      outbus);

  initial begin
    #000 inbus = 32'hffff0000; busen_ = 1'b1;
    #100 inbus = 32'h0000ffff; busen_ = 1'b0;
    #100 inbus = 32'h00ff5500; busen_ = 1'b0;
    #100 $finish;
  end
endmodule

Regards - Cliff Cummings - cliffc@tekeda.pen.tek.com

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