🚀 go-pugleaf

bjdunlop@shamash.cdc.com (Bruce Dunlop) writes:
: 
: A company called Chronologic Simulation was mentioned as having a fast
: verilog compiler, in a previous post here.  Can someone give me their
: phone number?
: 
: Also, does anyone have any good/bad experiences with it?
: 

Contact:
  Craig Combes
  Chronologic
  (415)965-3312

jwest@wisc (Jeff West) writes:

>bjdunlop@shamash.cdc.com (Bruce Dunlop) writes:
>: 
>: A company called Chronologic Simulation was mentioned as having a fast
>: verilog compiler, in a previous post here.  Can someone give me their
>: phone number?
>: 
>: Also, does anyone have any good/bad experiences with it?
>: 

>Contact:
>  Craig Combes
>  Chronologic
>  (415)965-3312

Fintronic claims to have a very fast Verilog simulator.  Contact Alec
Stanculescu (alec@fintronic.com), (415) 325-4474.

Larry

In article <49596@shamash.cdc.com> bjdunlop@shamash.cdc.com (Bruce Dunlop) writes:
>A company called Chronologic Simulation was mentioned as having a fast
>verilog compiler, in a previous post here.  Can someone give me their
>phone number?  Also, does anyone have any good/bad experiences with it?

A previous poster supplied the phone number, but I'll offer some comments.
Chronologic Simulation just went into production with their VCS (Verilog  
Compiled Simulator) and KPCI was one of several companies that participated
in the Beta testing.  Chronologic says that, with VCS, simulation execution 
time is sped up over Verilog-XL by a factor of 10-20 for typical RTL 
(synthesizable) models and up to 40 for pure behavioral models.  

We have tried several different simulations, all at the RTL level, and have
indeed seen 10-20x speedups over Verilog-XL.  We are now running a model 
with a 16x speedup, which pulls a nearly intolerable 12 hour simulation
down to well under an hour.  This fundamentally changes the way we can
approach the design verification process.  We have also seen VCS memory 
usage as little as one-tenth that of Verilog-XL.

VCS does not (yet) contains all the functionality of Verilog-XL, although
it took us only an hour or two to massage our model to work under VCS.
The main limitations are that it does not provide an interactive mode nor
all the PLI routines necessary to link to some third-party models.  But
given the performance gains we have seen, we are highly motivated to find 
workarounds to make VCS a part of design verification on future projects.

						Tom Anderson

In article <1992Nov17.032709.7216@kpc.com>, tla@kpc.com (Tom Anderson) writes...
>In article <49596@shamash.cdc.com> bjdunlop@shamash.cdc.com (Bruce Dunlop) writes:
>>A company called Chronologic Simulation was mentioned as having a fast
>>verilog compiler, in a previous post here.  Can someone give me their
>>phone number?  Also, does anyone have any good/bad experiences with it?
> 
>A previous poster supplied the phone number, but I'll offer some comments.
>Chronologic Simulation just went into production with their VCS (Verilog  
>Compiled Simulator) and KPCI was one of several companies that participated
>in the Beta testing.  Chronologic says that, with VCS, simulation execution 
>time is sped up over Verilog-XL by a factor of 10-20 for typical RTL 
>(synthesizable) models and up to 40 for pure behavioral models.  
> 
>We have tried several different simulations, all at the RTL level, and have
>indeed seen 10-20x speedups over Verilog-XL.  We are now running a model 
>with a 16x speedup, which pulls a nearly intolerable 12 hour simulation
>down to well under an hour.  This fundamentally changes the way we can
>approach the design verification process.  We have also seen VCS memory 
>usage as little as one-tenth that of Verilog-XL.
> 
>VCS does not (yet) contains all the functionality of Verilog-XL, although
>it took us only an hour or two to massage our model to work under VCS.
>The main limitations are that it does not provide an interactive mode nor
>all the PLI routines necessary to link to some third-party models.  But
>given the performance gains we have seen, we are highly motivated to find 
>workarounds to make VCS a part of design verification on future projects.
> 
>						Tom Anderson