Memory Addressing in verilog

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2 total messages Started by Steve Wood Wed, 18 Nov 1992 18:19

#138

Author: Steve Wood
Date: Wed, 18 Nov 1992 18:19

20 lines
1437 bytes

I am trying to write a behavioural model for a family of modular 1- and
2-port memories and am new to the verilog language.  

I have been experimenting with "writing" (i.e. procedural assignment to
a memory register array) to the memory array with array index (address) set to "X".
Such a condition is a serious error in a real memory, however verilog seems
to ignore any out of range or unknown index when it is part of the LHS of a
procedural assignment.

My question is: does verilog do any bounds checking on index values to register
                arrays or do I have to implement such checks myself?
-- 
regards,

============================================================================================
Steven Wood			Phone: 613-763-2830
Memory Development		ESN:     6-393-2830
Bell Northern Research          Email: swood@bnr.ca (internet)
============================================================================================

Memory Addressing in verilog

#140

Author: Elliot H. Mednick
Date: Thu, 19 Nov 1992 15:44

31 lines
1855 bytes

In article <1992Nov18.181933.10242@bcrka451.bnr.ca> swood@bnr.ca writes:
 > My question is: does verilog do any bounds checking on index values to register
 >                 arrays or do I have to implement such checks myself?

You have to implement the checks yourself.  Note that in RTL coding, you
don't want to do checking unless the hardware you are designing is going to
do range-checking.  In behavioral-level coding, you can do whatever you want.

One technique that you ca use is to have a seperate "integrity-check"
module that continually tests things like index ranges and detects
other illegal conditions.  This module would be a 2nd top-level module
(that is, niether of the top-level module instantiate each other) and
reference variables within the simulation model by hierarchical names
so it would be non-intrusive.  This way, you can have an RTL model,
perhaps for synthesis, but with the range checking not part of the
actual RTL model.  For example:

module integrity;

// monitor 'index'
always @(my_module.index)
  if (my_module.index < 0 || my_module.index > `MAX_INDEX)
     $display ("Index out-of-bounds detected at time %t!", $time);
...
endmodule

--
Elliot H. Mednick                                        P.O. Box 150
Wellspring Solutions                                     Sutton, MA. 01590
elliot@Wellspring.com                                    +1 508 865 7271

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