🚀 go-pugleaf

Due to popular demand, Qualis Design Corporation will begin offering its
High Level Design Courses in Santa Clara, CA, beginning in April.  Since some
of our clients have advanced bookings, we expect these popular courses to
fill quickly -- if you plan to attend, contact us immediately to reserve your
space!

The Santa Clara course schedule for April and May, 1996, is:

       Course Title                        Course Dates
       ----------------------------------------------------------
       High Level Design Using Verilog:    April 15-19
                                           May 13-17

       High Level Design Using VHDL:       April 29-May 3
                                           May 20-24

       Advanced Techniques Using Verilog:  April 24-26

       Advanced Techniques Using VHDL:     May 15-17

For information about the material covered in these courses, see the course
descriptions below.

The Qualis Difference
---------------------
We know what it's like to work under the pressure of aggressive schedules and
immense technical challenges.  We believe that High Level Design methods
and technology, such as HDL-based verification and synthesis, are
the key to tackling those challenges and conquering today's design problems.
We want to make a difference in your life and career by teaching you the
latest in High Level Design.  Here's how we do it:

 -- The Qualis "Best In Class" Instructor Team draws upon the absolute best
    Verilog and VHDL consulting and training talent in the industry.  Our
    instructors, top-notch Engineers with up-to-date experience, know how
    to relate the course material to your real-world design problems.

 -- Our courses are intense, hands-on events using the latest EDA tools
    and hardware.  Everything you need to learn quickly and efficiently is
    provided -- you supply the brain, we'll supply everything else.

 -- Our courses are like no other in the EDA industry.  Engineers and
    Managers who attend our courses will learn what's important and why, and
    where to focus their time and resources for maximum leverage from HDLs
    and design tools.

New for 1996!
-------------
Qualis is teaming-up with Chip Express, the leader in ASIC Time-to-Market
Solutions, in 1996 with technology support in Qualis' High Level Design
Using Verilog and VHDL courses.  All students who successfully complete a
Qualis High Level Design course will receive a coupon good for 75% off the
cost of their first Chip Express laser gate-array prototypes!  Call us
for more details.

About Qualis Design Corporation
-------------------------------
Founded in 1992, Qualis Design Corporation has quickly become the
leading independent provider of High Level Design consulting and
training services.  The company provides services to leading-edge high
technology firms worldwide, including Intel, Hewlett-Packard,
Tektronix, Xerox, TRW, Northern Telecom and Bell-Northern Research.
Qualis' corporate headquarters are located in Beaverton, Oregon.

Don't miss this opportunity to learn the latest in High Level Design from
the best in the industry.  For course syllabi and registration information,
contact us at:

                           Qualis Design Corporation
                    15455 NW Greenbrier Parkway, Suite 250
                       Beaverton, Oregon 97076-4444 USA

                            Phone: +1-503-531-0377
                             FAX: +1-503-629-5525
                         E-mail: training@qualis.com
                         World Wide Web: coming soon!


Brief Course Descriptions
--------------------------

                   High Level Design Using Verilog
                    High Level Design Using VHDL

            Copyright (c) 1995, 1996 Qualis Design Corporation

"High Level Design Using Verilog" and "High Level Design Using VHDL"
are fast paced, 5-day hands-on, multimedia courses designed not only
to teach High Level Design techniques and the Verilog and VHDL
languages, but to make class participants immediately productive in
a system design environment using state-of-the-art simulation and
synthesis tools.  Each course addresses their respective language
exclusively.

After an introduction to [Verilog/VHDL], the course deviates from the
traditional bottom-up, gates-to-behavioral modeling presentation of
other [Verilog/VHDL] courses and reverses the flow, teaching top-down
design practices, with early special emphasis on coding for synthesis,
efficient testbench generation and advanced design verification
techniques. These skills are reinforced throughout the week while
teaching [Verilog/VHDL] from a High Level Design perspective.

The course labs are designed to accommodate the learning aptitudes of
a wide range of students with diverse design experiences. Each lab is
structured into three parts:

     1.        Fundamental Concepts Review and Experience
     2.        Recognition of Common Mistakes and Correcting Problems
     3.        Additional Material for Advanced Students

All students complete parts one and two of each lab.  Part three is
for students who finish early and want to learn additional material.
This lab structure caters to all student skill levels and provides
excellent opportunities to expand one's knowledge of [Verilog/VHDL]
simulation and synthesis techniques.

Each day of class is divided into multiple interactive lecture and
lab sessions.  Students have access to individual Sun Sparcstations,
the [Verilog/VHDL] simulation environment of their choice, and the
Synopsys DC Expert synthesis environment for use during the lab
sessions.  The course material is presented using a projection system
that allows 30% more material to be presented in a given amount of
time with vivid, interest-grabbing color slides.

------------------------------------------------------------------------------

                  Advanced Techniques Using Verilog
                   Advanced Techniques Using VHDL

                          Course Overview

             Copyright (c) 1996 Qualis Design Corporation

The courses "Advanced Techniques Using Verilog" and "Advanced
Techniques Using VHDL" are fast paced, 3-day hands-on, multimedia
courses designed to bring Engineers with experience in using
Verilog and VHDL to an unparalleled level of efficiency.  Each
course addresses their respective language exclusively.

After a review of the more advanced behavioral constructs and
features of [Verilog/VHDL], the course immediately illustrates
how these constructs can turn an ordinary-looking environment
into a design simulation and verification powerhouse through
the use of bus-functional models, test harnesses, abstract
regressionable testbenches and behavioral models.

Each day of class includes interactive lecture sessions with
8 challenging labs.  Students will have access to individual Sun
Sparcstations and the [Verilog/VHDL] simulation environment of their
choice.  The course material is presented using a projection
system that allows 30% more material to be presented in a given amount
of time with vivid, interest-grabbing color slides.

Student Questions
-----------------
Prior to the first day of the courses, registered students are
encouraged to submit questions related to their current usage
of [Verilog/VHDL] to the instructor.  Questions or topics that
illustrate modeling techniques or features of the language will
be included in the course presentation.

Course Prerequisites
--------------------
Students are expected to have prior experience with the
[Verilog/VHDL] language, or previously attended the Qualis course
"High-Level Design Using [Verilog/VHDL]".  Knowledge of a structure
programming language, such as C or Pascal, is recommended.

------------------------------------------------------------------------------

                           Qualis Design Corporation
                    15455 NW Greenbrier Parkway, Suite 250
                       Beaverton, Oregon 97076-4444 USA

                            Phone: +1-503-531-0377
                             FAX: +1-503-629-5525
                         E-mail: training@qualis.com
                         World Wide Web: coming soon!

Copyright (c) 1995, 1996, Qualis Design Corporation.  All Rights Reserved.

"DC Expert" is a trademark of Synopsys, Inc.
"Verilog" is a registered trademark of Cadence Design Systems, Inc.
"The ASIC Time-to-Market Solution" is a trademark of Chip Express Corp.