🚀 go-pugleaf

In article <rfall-240992171955@andrich.mv.us.adobe.com>, rfall@mv.us.adobe.com (Richard Fall) writes:
> Does anyone know if there's an easy way of doing the following
> in Verilog?
> 
>     I would like to be able assign a fixed value (say, zero),
>     declared as a single parameter ("zero") in assignment
>     statements where the variable on the LHS of the statements
>     may be of different bit width.
>     
> ...
> 
>     Before you rush to tell me that Verilog already does that
> by zero-extending the RHS side to fit the LHS side, I'll point
> out that I may want to do the same thing with a parameter in
> which zero-extending is not the correct behavior.  For
> example, I may want the value "5555...." to be assigned to
> registers that may be any multiple of 4 bits wide.
> 

besides doing zero-extension, verilog also does automatic truncation.

thus you can define:

parameter fives = 64'h5555555555555555;

and then assign it to a lhs of any width <= 64.  the extra bits will simply
be discarded.

-- 

    Cindy Eisner,                     Tel: 972-4-551551
    CAD group,                        Fax: 972-4-551550
    Zoran Microelectronics LTD,       E-mail: cindy@Zoran.HellNet.Org
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