🚀 go-pugleaf

In article <rfall-240992171955@andrich.mv.us.adobe.com> rfall@mv.us.adobe.com writes:
 >     I would like to be able assign a fixed value (say, zero),
 >     declared as a single parameter ("zero") in assignment
 >     statements where the variable on the LHS of the statements
 >     may be of different bit width.
 >
 > [example omitted]
 > 
 >     Before you rush to tell me that Verilog already does that
 > by zero-extending the RHS side to fit the LHS side, I'll point
 > out that I may want to do the same thing with a parameter in
 > which zero-extending is not the correct behavior.  For
 > example, I may want the value "5555...." to be assigned to
 > registers that may be any multiple of 4 bits wide.
 > 
 >     If there were a "sizeof" operator, this would be easy
 > to do by using it in conjunction with repeated concatenation
 > to produce the desired effect, but no such operator appears to
 > exist.

There isn't a "sizeof" operator, but there is no reason for one since the
length of the lvalue is always known and almost always easily determined.
What you want (if I understand the question correctly) is some variation
on the following:

`define smallsize 4
`define longsize 16
parameter constant = 1'h5;

reg [`smallsize-1:0] foo;
reg [`longsize-1:0] foolong;
...
foo = {`smallsize/4 {constant}};
foolong = {`longsize/4 {constant}};
...

Note that this will only work for sizes that are multiples of the radix
size.  If you need sizes that are not multiples, then define a long constant
which is the largest you would ever need and use it for everything (Verilog
will truncate as necessary):

`define longsize 64             // in bits
parameter constant = 1'h5;
paramater longconstant = {`longsize/4 {constant}};
...
foo = longconstant;
foolong = longconstant;
fooverylong [58:0] = longconstant;
...

Both examples are synthesizable.