🚀 go-pugleaf

In article 8369@tekig7.PEN.TEK.COM, cliffc@tekeda.PEN.TEK.COM (Clifford E Cummings) writes:
> In article <C17p8K.7nA@iphase.com> phan@iphase.com (Tai Phan) writes:
> >If anyone knows a simple way to describe in Verilog an Open collector, 
> >Inverted, with Output enable bus, please help.  The parameters are as follow:
> >

Stuff deleted...

> Is this what you are looking for? (this example can be run)
> 
> `timescale 1ns/100ps
> module oc_bus( outp_, inp, oen_);
>   // Verilog code
>   input [31:0] inp;               // Input bus
>   input oen_;                     // Output enable
>   output [31:0] outp_;            // Output bus
> 
>   triand (strong1, highz0) [31:0] outp_ = (~oen_ ? ~inp : 32'bz);


I believe it should be:

triand (highz1, strong0) [31:0] outp_ = (~oen_ ? ~inp : 32'bz);


> 
> endmodule
> 
> module oc_bus_test;

Stuff deleted...

> endmodule
> 
> Regards - Cliff Cummings - cliffc@tekeda.pen.tek.com




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Chandresh Patel			Amdahl Advanced Systems, Fremont CA
patel@key.amdahl.com