🚀 go-pugleaf

smb@afterlife.ncsc.mil (Steve M. Burinsky) writes:

> I need to simulate delay lines in order to model a bus interface.  The
> solution seems obvious --  use a net delay.  However, the signal I need
> to delay has pulse widths (w) which are shorter than the delay time (d);
> that is w < d.  The problem is that inertial delay causes the short pulse
> to disappear within the delay.

If you do not expect to have more than a single pulse (2 edges) every delay time
d units, then you could use the pulse rejection ratio command line switches
to Verilog. I do not have a manual in front of me now to give you the details, 
but it is something like +pulse_r. This will however, change the pulse swallowing
ratio for all delays in the design. If you want control on one specific delay, 
then look into using the specparam based control on pin-to-pin delays. The section
on specify blocks in the manual talks about this.
But the problem we ran into was we needed to run multiple pulses into the
delay line such that n*w < d, where n was the number of pulses. So we should
have seen all the n pulses come out of the delay line after a delay of d.
The switches mentioned above will let you control the width of a pulse that 
will get thru but not the number of pulses. Verilog-Xl will only let you 
schedule at the most 2 events (I believe) on any node. Each new event after the
second one will cause an earlier scheduled event to get overwritten/dropped.
As a result Verilog will show you only the last pulse in the pulse train 
come out of the delay line. For this problem, I believe there is no solution
other than using a string of elements to build the delay line.

---
Rajesh Patil
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Advanced Product Operations                 rajesh@chdasic.sps.mot.com
Motorola ASIC				     ----------------------------------------------------------------------