Re: NDL => Verilog Translator

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Article #71

#71

From: Julian Fields
Date: Sat, 29 Aug 1992 00:13

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hutton@eucad.co.uk (Peter Hutton) writes:
>Has anyone heard of (or even better got) a translator from LSI Logic's NDL
>format to Verilog? Sources, names, contacts, hints ... all welcome.

Synopsys can do this if you want all the gates instantiated.

-- 
Julian Fields, Jr        fields@acuson.com  
VLSI Design Engineering Consultant 
415-929-9112x2408 work,408-773-8197h
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Path: arc1-ca.pugleaf.net!sparky!uunet!kithrup!stanford.edu!ames!sun-barr!male.EBay.Sun.COM!exodus.Eng.Sun.COM!sun!amdcad!sono!fields
From: fields@acuson.com (Julian Fields)
Newsgroups: comp.lang.verilog
Subject: Re: NDL => Verilog Translator
Keywords: NDL Verilog
Message-ID: <1992Aug29.001334.27619@acuson.com>
Date: 29 Aug 92 00:13:34 GMT
References: <1992Aug26.111539.6772@Cadence.COM>
Organization: Acuson; Mountain View, California
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