Re: verilog and synthesis

Article View: comp.lang.verilog

Article #149

#149

From: John Cooley
Date: Sun, 13 Dec 1992 04:08

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From: ekenberg@down.hep.upenn.edu (Tor L. Ekenberg)

> I am looking for information about using Verilog for synthesis. I guess
> something about what constructs are prefered, if there are some
> companies that provide tools, etc. I am completely new to the field
> of synthesizable Verilog so any information will be useful.

Tor, you may wish to join the E-mail Synopsys User Group (ESNUG) if
your company already owns a copy of Synopsys.  You'll find we discuss
issues just like you're asking.  To join, all you have to do is send
me e-mail expressing an interest in subscribing.

                                               - John Cooley
                                                 ESNUG Moderator


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Newsgroups: comp.lang.verilog
Path: arc1-ca.pugleaf.net!sparky!uunet!world!jcooley
From: jcooley@world.std.com (John Cooley)
Subject: Re: verilog and synthesis
Message-ID: <Bz6JHt.29C@world.std.com>
Organization: The World Public Access UNIX, Brookline, MA
Date: Sun, 13 Dec 1992 04:08:16 GMT
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