🚀 go-pugleaf

gotom@hpysoln.tky.hp.com (Masaharu Goto) writes:



>Commercial availability of the Verilog <-> VHDL translators 

>	Cadence	VDOC-454	Verilog to VHDL translator
>		 Cadence is the originator of the Verilog-HDL and it seems
>		like VDOC-454 has a quite good coverage on Verilog to VHDL
>		translation.  It costs $200k~300k.
>		 It translates User Defined Primitives and architectural
>		description very good.  Now, I am giving my benchmark example 
>		to see how good it translates behavioral Verilog description 
>		to VHDL. I will let you know when their benchmark comes out.
>		 I am not sure if they have VHDL to Verilog translator.

   Does anyone know what this tool does with the "tran" primitive?  I am
having difficulty finding a way to model this in VHDL.

--
George Lippincott