Article View: comp.lang.verilog
Article #85legality of force?
From: Charles Robert Yount
Date: Fri, 02 Oct 1992 20:45
Date: Fri, 02 Oct 1992 20:45
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I'm trying to find out what's legal on the lhs of a force statement. I have the following: module romp; . . wire [0:31] alu_a; . . endmodule force romp.alu_a[2] = 1'b1; <-- gives error; illegal lhs force romp.alu_a = 1'b1; <-- is ok. Why won't the first one work? Is there another way to force the value of one bit? Thanks in advance! Chuck Yount, CMU ECE
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arc1-ca.pugleaf.net!sparky!uunet!convex!darwin.sura.net!zaphod.mps.ohio-state.edu!cis.ohio-state.edu!news.sei.cmu.edu!fs7.ece.cmu.edu!fs7!yountShow Full Headers
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Newsgroups: comp.lang.verilog Path: arc1-ca.pugleaf.net!sparky!uunet!convex!darwin.sura.net!zaphod.mps.ohio-state.edu!cis.ohio-state.edu!news.sei.cmu.edu!fs7.ece.cmu.edu!fs7!yount From: yount@fox.ece.cmu.edu (Charles Robert Yount) Subject: legality of force? Message-ID: <YOUNT.92Oct2154553@fox.ece.cmu.edu> Sender: news@fs7.ece.cmu.edu (USENET News System) Organization: Electrical and Computer Engineering, Carnegie Mellon Distribution: comp Date: Fri, 2 Oct 1992 20:45:53 GMT Lines: 22