Article View: comp.lang.verilog
Article #40parameters
From: Gord Wait
Date: Fri, 03 Apr 1992 22:20
Date: Fri, 03 Apr 1992 22:20
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1790 bytes
In article <1992Mar30.211350.14338@ncsu.edu> hdeshma@eos03a-16pa.eos.ncsu.edu (HARSHAVARDHAN DESHMANE) writes:
>
>although the parameter declaration is intuitive to use,
>can the same things be done by declaring the parameters
>to integers?
>In what way is a 'parameter' different from an integer? Sorry
>if this sounds silly, but I am unclear about the real reason
>for the declaration.
>
>harsh
>________________________________________________________________________________
>Harshavardhan Deshmane * no fancy stuff*
>ECE Dept, North Carolina State University
>________________________________________________________________________________
For one thing, parameters can be altered when you instantiate a model.
For example:
module testparams;
parameter p1 = 5;
parameter p2 = 8;
initial
begin
$write("p1 is %d, p2 is %d\n", p1, p2);
end
endmodule
Now when you use it you can change the values of P1 and P2 like this:
module junk;
item1 testparams;
item2 #(1, 2) testparams;
item3 #(9,10) testparamsl
endmodule
In the above example item1 will print out the original values of 5 and
8, item2 will print out values of 1 and 2, and item three will print
out values of 9 and 10 for the p1 and p2 parameters. RTFM, page 12-8
volume 1 of Cadence Verilog 1.6.0.1
Gord
--
Gord Wait SMOS Systems Vancouver Design Centre
uunet!jericho!gord
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Newsgroups: comp.lang.verilog Path: arc1-ca.pugleaf.net!sparky!uunet!jericho!gord From: gord@jericho.uunet.uu.net (Gord Wait) Subject: parameters Message-ID: <1992Apr3.222032.11639@jericho.uunet.uu.net> Sender: gord@jericho.uunet.uu.net (Gord Wait) Organization: S-MOS Systems, Inc. (Vancouver Design Center) Date: Fri, 3 Apr 1992 22:20:32 GMT