Article View: comp.lang.verilog
Article #42converting verilog pin states to GenRad Tester
From: Robert Larrivee
Date: Thu, 09 Apr 1992 10:32
Date: Thu, 09 Apr 1992 10:32
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890 bytes
I am looking for a way to convert verilog pin states to a GenRad DTS(digital test source). The DTS is for an incircuit machine. We are looking at creating a PLI routine, using the vcd file (verilog common dump), or creating a task to monitor when the pins changed state. Monitoring the states would be easy but verilog does not have a "sense" state as a tester does, so it doesn't know when a bidir is driving or receiving. Thanks for any info!!! Bob
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Path: arc1-ca.pugleaf.net!sparky!uunet!usc!rpi!bu.edu!transfer!corwin.hw.stratus.com!rml From: rml@corwin.hw.stratus.com (Robert Larrivee) Newsgroups: comp.lang.verilog Subject: converting verilog pin states to GenRad Tester Keywords: tester Message-ID: <2035@transfer.stratus.com> Date: 9 Apr 92 10:32:13 GMT Sender: usenet@transfer.stratus.com Followup-To: rml@corwin.hw.stratus.com Organization: Stratus Computer, Inc. Lines: 8