specify blocks

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Article #45

#45

From: Ken Hanson
Date: Sat, 11 Apr 1992 23:13

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I am new to the verilog HDL, and am looking for a better description of 
the use of specify blocks.  It appears to me that they are used to 
force time constraints on signal propagation in a module.   And when
a constraint has been reached a signal reg variable may be set to indicate
this.  Is this correct?  Are there any other purposes to specify blocks,
any good examples of thier use?  Any help would be appreciated.


	  -- Ken Hanson (hanson@henson.cc.wwu.edu)

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Path: arc1-ca.pugleaf.net!sparky!uunet!cs.utexas.edu!uwm.edu!ogicse!henson!hanson
From: hanson@henson.cc.wwu.edu (Ken Hanson)
Newsgroups: comp.lang.verilog
Subject: specify blocks
Summary: purpose of specify blocks
Keywords: verilog
Message-ID: <1992Apr11.231312.3546@henson.cc.wwu.edu>
Date: 11 Apr 92 23:13:12 GMT
Article-I.D.: henson.1992Apr11.231312.3546
Organization: Western Washington University
Lines: 9