🚀 go-pugleaf

In article <1992Apr11.231312.3546@henson.cc.wwu.edu> hanson@henson.cc.wwu.edu (Ken Hanson) writes:
>I am new to the verilog HDL, and am looking for a better description of 
>the use of specify blocks.  It appears to me that they are used to 
>force time constraints on signal propagation in a module.   And when
>a constraint has been reached a signal reg variable may be set to indicate
>this.  Is this correct?  Are there any other purposes to specify blocks,
>any good examples of thier use?  Any help would be appreciated.
>
>
>	  -- Ken Hanson (hanson@henson.cc.wwu.edu)

Specify blocks are used to specify timing constraints and timing checks.
Another very common use is "specparams"  They are variables that can be
read via the PLI routines and used for back annotating information back
into the verilog data structure.  Such as input/output capacitance, drive
strenghts and other cell dependant specifications.  For more details
on this look in the PLI reference manual and the example delay calculators
that ship with Verilog.