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Article View: comp.lang.verilog
Article #50

Re: Analogue modeling by Verilog

#50
From: Steven Greenberg; x6231
Date: Tue, 08 Sep 1992 17:49
13 lines
1119 bytes
Analog modelling is not Verilog's forte, but it can be done.  In fact, if you
order the mixed-signal product with Analog Artist, you get some analog
behavioral models in Verilog.

I don't claim to be a Verilog modelling expert, but I once wrote a vco model
in Verilog to prove to some people that it could be done.

To pass an analog value into a Verilog module, you have to create a 64-bit wire
port.  You then use system functions like $bitstoreal to convert the wire at
the port to a real number inside the module.  Once you have real numbers inside
the module, you can do anything you want.

/Steve
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Message-ID: <1992Sep8.174925.6747@Cadence.COM>
Path: arc1-ca.pugleaf.net!sparky!uunet!Cadence.COM!popeye!steveg
References: <1992Sep3.071552.9412@uxmail.ust.hk>

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Newsgroups: comp.lang.verilog
Path: arc1-ca.pugleaf.net!sparky!uunet!Cadence.COM!popeye!steveg
From: steveg@popeye.cadence.com (Steven Greenberg; x6231)
Subject: Re: Analogue modeling by Verilog
Message-ID: <1992Sep8.174925.6747@Cadence.COM>
Sender: usenet@Cadence.COM (Usenet News)
Nntp-Posting-Host: popeye
Reply-To: steveg@popeye.cadence.com (Steven Greenberg; x6231)
Organization: Cadence Design Systems, Inc.
References:  <1992Sep3.071552.9412@uxmail.ust.hk>
Date: Tue, 8 Sep 1992 17:49:25 GMT
Lines: 13