Re: Summary of designing ASIC using Verilog

Article View: comp.lang.verilog

Article #62

#62

From: Interpretive Systems
Date: Wed, 12 Aug 1992 22:49

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In article <1992Aug12.180805.13962@informatik.uni-hamburg.de> fan@tech9.informatik.uni-hamburg.de (Xiaoming Fan) writes:
>bout three weeks ago I posted the message asking about designing ASIC using
>Verilog. So far I  did not receive  many responses.  Any new information or
>comments would also be appreciated.
>3. From: marchior@dxcern.cern.ch (Alessandro Marchioro)
>
> 1- Verilog book: look for 
>     E. Sternheim et al.
>     Hardware Modeling with Verilog HDL
>                    Automata Publishing Company
>                    POBox 50335             !!!!!! Wrong (old)
>                    Palo Alto  CA 94303     !!!!!! Wrong (old)
>                    fax: (415) 855 9545     !!!!!! Wrong (old)

The new address for Automata Publishing Co. is

10487 Westacres Dr.
Cupertino, CA 95014
Tel (408) 255-0705
FAX (408) 253-7916

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Newsgroups: comp.lang.verilog
Path: arc1-ca.pugleaf.net!sparky!uunet!decwrl!csus.edu!netcom.com!eli
From: eli@netcom.com (Interpretive Systems)
Subject: Re: Summary of designing ASIC using Verilog
Message-ID: <+84m3-p.eli@netcom.com>
Date: Wed, 12 Aug 92 22:49:50 GMT
Organization: Netcom - Online Communication Services  (408 241-9760 guest) 
References: <1992Aug12.180805.13962@informatik.uni-hamburg.de>
Keywords: Verilog, Cadence, ASIC
Lines: 22

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