🚀 go-pugleaf

When thinking about modelling bi-directional devices like pass transistors and transmission gates for CMOS VLSI circuits, it struck me that VHDL does not have
a mechanism for identifying the driver responsible for an event. If the models
for such devices could identify that they had previously scheduled the events
which activated them then it would be possible to write simpler models for them.

What I had in mind was a signal attribute (e.g. 'DRIVER) which would be "true"
in the in the process(es) responsible for signal being active in a particular
cycle, and "false" in processes which did not schedule any transactions for that
cycle.

I hope this is a suitable place to discuss such issues - if not where?

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Kevin Cameron         INMOS, 1000 Aztec West, Almondsbury, Bristol BS12 4SQ, UK