🚀 go-pugleaf

In article <dank.724653378@blacks.jpl.nasa.gov>, dank@blacks.jpl.nasa.gov (Daniel R. Kegel) writes:
> Hi all,
> is there an accepted idiom for expressing the sort of timing checks
> supported in Verilog, i.e.
>     $width(negedge x, t0);
>     $setup(x, posedge y, t0);
>     $hold(posedge x, y, t0);
> in VHDL?
> 
> I'm thinking about converting a PD program that generates Verilog
> to also generate VHDL.
> - Dan Kegel (dank@blacks.jpl.nasa.gov)


----- News saved at 18 Dec 92 19:53:13 GMT

The VHDL Technology Group offers a set of VHDL packages
called the Std_DevelopersKit which provides a set of
equivalent timing check routines as provided by Verilog.
In addition, it also provides equivalent mathematical routines
and hundreds of additional functions which VHDL model developers
may need.

Anyone having interest in the Std_DevelopersKit should send
their request (including postal address and phone number) to
the address below and we will be happy to send you a brochure.


Sincerely,

-------------------------------------------------------------
William Billowitch                   e-mail: uunet!vhdl!wdb
The VHDL Technology Group                    vhdl!wdb@uunet.uu.net (internet)
100 Brodhead Road, Suite 140         Phone : 215-882-3130
Bethlehem, PA 18017                  Fax   : 215-882-3133