🚀 go-pugleaf

 I am not an expert on the subject, and not sure if I can give you an 
appropreate idea.  If my information is wrong, please ignore. I have no
confidence on this, just an idea. 

 But the difference between Verilog and VHDL seems like Port Collapsing. 
Verilog manual says it Verilog-XL simulator collapses port connections
whenever possible. And no special declaration is needed for collapsing nets.
While,(though I am not too sure) in VHDL , if you want to collapse nets
you need to declare the net type of "Buffer". So, I imagine one of the
bidirectional signal has to be "Buffer" type. (Do I understand correct?
VHDL expert, please correct if I am wrong.)
 However, an example of "Buffer" usage I've seen is different from your
situation.