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Article View: comp.lang.vhdl
Article #320

Re: wire primitives in VHDL

#320
From: Daniel S. Barclay
Date: Mon, 28 Dec 1992 12:49
43 lines
3000 bytes
>  I am not an expert on the subject, and not sure if I can give you an 
> appropreate idea.  If my information is wrong, please ignore. I have no
> confidence on this, just an idea. 
> 
>  But the difference between Verilog and VHDL seems like Port Collapsing. 
> Verilog manual says it Verilog-XL simulator collapses port connections
> whenever possible. And no special declaration is needed for collapsing nets.
> While,(though I am not too sure) in VHDL , if you want to collapse nets
> you need to declare the net type of "Buffer". So, I imagine one of the
> bidirectional signal has to be "Buffer" type. (Do I understand correct?
> VHDL expert, please correct if I am wrong.)
>  However, an example of "Buffer" usage I've seen is different from your
> situation.

Well, port collapsing is not _the_ difference (there are many) ...

A VHDL simulator is allowed to collapse ports (or do whatever other 
optimization it wants) as long as it does not change the behavior of the 
model.  The language is defined (fairly) precisely so that (usually) a 
simulator can tell when it can optimize something. 

Using mode "buffer" may make it easier for a given simulator to optimize the 
simulation.  However, that doesn't mean that all simulators must require you
to use a specific mode to get optimized simulation, and neither does it mean
that using mode "buffer" will optimize simulation on all simulators.

Resolved ports in VHDL make port collapsing difficult.  Because of the signal 
resolution mechanism in VHDL, a simulator can't precisely collapse a resolved 
part unless the user tells the simulator that a given resolution function is 
suitable for collapsing.  (The resolution function must be commutative and 
associative (extended beyond two-argument functions).  In general, a simulator
cannot determine this by inspecting the function.)  A simulator could have a
flag set by the user to assume that resolution functions are collapsible; a
simulator might recognize resolution functions written in a certain form
(e.g., a lookup table) and inspect the table to determine if ports are
collapsible.

--
------------------------------------------------------------------------------
Daniel S. Barclay                    --who's still searching for a good 
CAD Language Systems, Inc.           signature, not liking any of his recent
Suite 101, 5457 Twin Knolls Rd.      feeble attempts to improve on the whiny:
Columbia, MD  21045  USA             Why can't _I_ think of a good signature?
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Message-ID: <DANIEL.92Dec28124951@algol.clsi.COM>
Path: arc1-ca.pugleaf.net!sparky!uunet!clsi!daniel
References: <1992Dec22.014551.24293@ole.cdac.com> <4380003@hpysoln.tky.hp.com>

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Newsgroups: comp.lang.vhdl
Path: arc1-ca.pugleaf.net!sparky!uunet!clsi!daniel
From: daniel@clsi.COM (Daniel S. Barclay)
Subject: Re: wire primitives in VHDL
In-Reply-To: gotom@hpysoln.tky.hp.com's message of Wed, 23 Dec 1992 17:12:10 GMT
Message-ID: <DANIEL.92Dec28124951@algol.clsi.COM>
Sender: usenet@clsi.COM
Organization: CAD Language Systems Inc.
References: <1992Dec22.014551.24293@ole.cdac.com> <4380003@hpysoln.tky.hp.com>
Date: 28 Dec 92 12:49:51
Lines: 44