MCC, VHDL

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Article #321

#321

From: Prince of Wales
Date: Mon, 28 Dec 1992 20:10

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Hi folks,

I am using the MCC compiler/simulator to compile a VHDL file. When I have
the following line in the source file, the compiler complains that the range
has to be inside the ANSI C bounds of --2147483647 to +2147483647, which is
slightly bigger than 1E05. The LRM for VHDL defines that the minimum 
acceptable limits for any compiler are -1E38 to +1E38. Is there a catch
somewhere or is it purely a limitation of the MCC system.

Thanks in advance.

-- 
ramanand@pumpkin.ece.uc.edu          home:   513 281 9870
rmandaya@uceng.uc.edu                office: 513 556 3025
mandayrv@ucunix.san.uc.edu           ham:    KB8GKL

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Newsgroups: comp.lang.vhdl
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From: mandayrv@ucunix.san.uc.edu (Prince of Wales)
Subject: MCC, VHDL
Message-ID: <BzzK1s.FFB@ucunix.san.uc.edu>
Organization: University of Cincinnati
Date: Mon, 28 Dec 1992 20:10:40 GMT
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