Wanted: VHDL to Verilog Translator

Article View: comp.lang.vhdl

Article #336

#336

From: Dom Paniscotti
Date: Fri, 20 Nov 1992 21:24

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Does anyone know where I could find a behavioural VHDL to
Verilog translator?  or possibly a yacc grammar for VHDL? 

                Thanks in advance,
                        Dom

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Path: arc1-ca.pugleaf.net!sparky!uunet!dtix!darwin.sura.net!jvnc.net!badboy.protocol.zycad.com!dominick
From: dominick@protocol.zycad.com (Dom Paniscotti)
Newsgroups: comp.lang.vhdl,comp.lang.verilog
Subject: Wanted: VHDL to Verilog Translator
Keywords: VHDL Verilog translator
Message-ID: <1ejl2bINNlq5@hayaku.protocol.zycad.com>
Date: 20 Nov 92 21:24:27 GMT
Sender: dominick@hayaku.protocol.zycad.com
Reply-To: dominick@protocol.zycad.com
Organization: Protocol, a Division of ZYCAD Corporation
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