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Subject: Verilog-HDL to VHDL translator

 Does anyone have information or experience about Verilog-HDL to VHDL 
translator?  

 My situation is

 I am designing an IC using Verilog-XL simulator.  On the other hand 
We will buy Mentor QuickSim2 for PC board simulation. It is very nice if
I could simulate the PC board with QuickSim2 including IC behavior model I 
write in Verilog.
 We will start the board simulation next April. I don't require
full timing simulation. Bulk delay simulation or even unit delay simulation
is still OK.  This time, purpose of the trial is pilot run of the Mentor
system rather than design verification itself. 

 Any kind of information/suggestions are appreciated.