🚀 go-pugleaf

Is there anybody out there with a VHDL description of a CMOS standard
cell library?

We are using VHDL to describe and simulate our designs. These designs
will be fabricated by ES2 (European Silicon Structures) a European
ASIC foundry. The actual fabrication will take place under the
EuroChip project. 

(The elements of a CMOS standard cell library are very similar and
thus we hope that we must merely adapt the propagation delays.
Furthermore the elements we are actually using are rather simple NAND,
NOR, EXOR, DFF with and without SET/RESET, TRI-STATE DRIVER and
MULTIPLEXOR. The standard cells of ES2 are designed in such a way that
post P&R back annotation doesn't play a big role, hence we would
accept to have this unsupported for now.)

Just as a question from a simple designer: 

Why aren't there any parameterisable CMOS standard cell library
descriptions available?  Thus that we need only a VHDL package with
the actual delays, setups and so on from the foundry. In the ancient
SILOS and HILO times this was the common way, the logic simulator
delivered the signal value set and the ``primitive models'' and the
silicon foundry the delays etc.  I guess that such a ``generic''
standard cell library would be a great improvement for the designers.
(and for the silicon foundries, obviously...)

To solve our problems we are thinking about the possibility to
annotate the ``VHDL SSI TTL'' component library available from
newell@itd.msstate.edu. 

Thanks in advance for any hints.

--
Klaus ten Hagen                | Aachen University of Technology
tenhagen@ert.rwth-aachen.de    | ERT -5240-
phone:+49 241 807632           | Templergraben 55
Fax:+49 241 807631             | D-5100 Aachen