🚀 go-pugleaf

Hello,
I am doing a chip-design at Trinity College
Dublin. The machine I work on is a DEC 5000/200 workstation, the
system is the cadence system EDGE with a MIETEC_2.4 um cell-library 
released by EUROCHIP.

I, or I should better say we, have got a problem with hierarchical
designs when simulating them with VERILOG. There are almost everytime
some unexpected compilation errors:

component name (<name>) not declared

For an example the message is : component name (I2a) is not declared.

In the netlist there is no "I2a" but there are Instances like
"AND2 I2(hnl_100, hnl_143);"

The error-message is described on page 20-13 in the Verilog-Manual. This error
only occurs when trying to simulate a hierarchical design. Sometimes
we can remove these compilation errors if we just copy a schematic and extract
it once more without any changes in the connectivity itself. But mostly, we 
get compilation errors with other undeclared nodes. Sometimes it really seems
to be random which nodes are not declared.
 
Having "caught" the temporary files verisave.cmdfile and verifoo.batch, we 
found that what was happening was that in certain random cases, the period
denoting the hierarchical position was omitted by either the Cadence 
Schematic capture or verilog.  However, the netlist generated by Cadence seems
to be okay.  Running the Verilog outside Cadence seems to work also.  We
suspect that the problem may be in the "runsim" section of the Simulation
Interface.  This "evidence" was found in verisave.cmdfile!
In the example above, for instance, I2a should have been I2.a but the period
got lost!  We caught the verisave.cmdfile by using the stepwise running of SI
in interactive mode during the runsim command.  Is there a patch for this
"bug"?  Is this reported elsewhere or by other users of Eurochip Releases?
Any relevant information would be appreciated!  Thanks in advance...



Rainer Hoehler
Eugene O' Rourke
orourke@mee.tcd.ie
rhoehler@mee.tcd.ie