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Article #440Re: VERILOG_PROBLEM
From: Colley M J
Date: Wed, 24 Jun 1992 08:41
Date: Wed, 24 Jun 1992 08:41
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1640 bytes
In article <1992Jun23.172809.1@vax1.tcd.ie> eorourke@vax1.tcd.ie writes: > >I, or I should better say we, have got a problem with hierarchical >designs when simulating them with VERILOG. There are almost everytime >some unexpected compilation errors: > >component name (<name>) not declared > At the University of Essex we are running Cadence EDGE 2.1 with the Mietec 2.4 um libraries on our HP/Apollo network (1 DN4000 and 4 Series 9000/400). We too have experienced this problem, and our investigations have led us to the same conclusion. We also found that if you edit the intermediate verilog files the simulation can then proceed as normal. We have not found a permanent solution to the problem, but replacing instances in the schematic does appear to remove the problem (albeit temporarily). We would also be interested to hear if there are any patches that will solve this problem. Martin Colley email: martin@essex.ac.uk
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 116545,b3c41b4b209d1de X-Google-Attributes: gid116545,public X-Google-Thread: 1089ad,b3c41b4b209d1de X-Google-Attributes: gid1089ad,public X-Google-ArrivalTime: 1992-06-23 23:52:56 PST Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!uknet!sersun1!csc8!martin From: martin@csc8.essex.ac.uk (Colley M J) Newsgroups: comp.lang.vhdl,eunet.esprit.eurochip Subject: Re: VERILOG_PROBLEM Message-ID: <4208@sersun1.essex.ac.uk> Date: 24 Jun 92 08:41:57 GMT References: <1992Jun23.172809.1@vax1.tcd.ie> Sender: root@sersun1.essex.ac.uk Reply-To: martin@essex.ac.uk (Colley M J) Organization: University of Essex, Colchester, UK Lines: 25