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2 total messages Started by Prince of Wales Sat, 02 Jan 1993 18:36
data types, vhdl
#328
Author: Prince of Wales
Date: Sat, 02 Jan 1993 18:36
29 lines
1312 bytes
Hi folks,

Is there any options in the vhdl language that lets me declare types
equivalent to the "union" in C. The brute force method that I can think of
is to declare a record with all the possible choices in the original union
as a strictly present field; and have integer tags to access the types: 

	e.g.	-- pseudo vhdl code;

	type union is record
		-- the tag to determine what field to use;
		access_type : integer;
		-- this is where the union starts
		-- list is declared earlier as an access type to a list;
		u1 : real;
		u2 : integer;
		u3 : list
		end record;

Is there any alternative to this lengthy  way of designing a data structure.


thanks for any replies and comments.

ramanand
-- 
ramanand@pumpkin.ece.uc.edu          home:   513 281 9870
rmandaya@uceng.uc.edu                office: 513 556 3025
mandayrv@ucunix.san.uc.edu           ham:    KB8GKL
Re: data types, vhdl
#410
Author: Daniel S. Barclay
Date: Mon, 04 Jan 1993 13:13
19 lines
1495 bytes
> Is there any options in the vhdl language that lets me declare types
> equivalent to the "union" in C. The brute force method that I can think of
> is to declare a record with all the possible choices in the original union
> as a strictly present field; and have integer tags to access the types: 
> ...

No.  There are no variant record types in VHDL.  Sorry.  

Your workaround is the best solution I know of if you need to declare signals
or constants of that type.  If you're working with variables only (e.g., in
one process), you can declare a record containing pointers to different types,
and then allocate data for only the type that's used.

--
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Daniel S. Barclay                    --who's still searching for a good 
CAD Language Systems, Inc.           signature, not liking any of his recent
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