Wanted: VHDL to Verilog Translator

Thread View: comp.lang.vhdl

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1 total messages Started by Dom Paniscotti Fri, 20 Nov 1992 21:24

#336

Author: Dom Paniscotti
Date: Fri, 20 Nov 1992 21:24

6 lines
733 bytes

Does anyone know where I could find a behavioural VHDL to
Verilog translator?  or possibly a yacc grammar for VHDL? 

                Thanks in advance,
                        Dom

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