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RE: Conversion of Verilog timing checks to VHDL?
From: William D. Billowitch
Date: Fri, 18 Dec 1992 20:06
Article: 313
Message-ID: <111@vhdl>
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- Subject: RE: Conversion of Verilog timing checks to VHDL?
- From: William D. Billowitch
- Date: Fri, 18 Dec 1992 20:06
- Article: 313