🚀 go-pugleaf

To the readers and participants of alt.lsi.cad:

Hi!
About a week ago, I posted a query about making
netlist comparisons (I was working with a program
which translated flattened lists to hierarchical
lists).

Thanks to the following who responded:

Carl Ketcham (c2k@ham.slc.mentorg.com)
? (petrot@masi.ibp.fr)
Martin Schlag (martine@cse.ucsc.edu)
Hank Walker (dmw@taurus.ece.cmu.edu)
Derek Beatty (Derek_Beatty@cmu.edu)
Mitchell Perilstein (clsi!mitch@uunet.UU.NET)
John Hayden (John-a.Hayden@Analog.Com)


Some asked more specific questions about the translator.

We have developed a timestep-driven mixed-mode simulator
which uses extremely accurate analytic macromodels for
many basic CMOS digital gates.  One can obtain *accurate*
waveform information in a mixed-mode circuit by running
an analog simulation of the whole circuit (which is,
of course, time consuming).  The analytic macromodels
allow us to partition the circuit in such a way as to
reduce the size of the analog circuit matrix (and thus
reduce the simulation time), but maintain the accuracy
(in the digital blocks) not provided by, say, event-driven 
digital simulators.  Strong feedback between the analog 
and digital blocks is not a problem.

Anyway, the purpose of the translator is to extract the
digital gates which can be represented by the macromodel,
and turn them into subcircuits.

I'm not sure exactly how this is done (I didn't write
the translator), but it seems like a pretty straightforward
parsing/comparison algorithm would do the trick.

To summarize the responses to the original question:

1) Use the Mentor Graphics CheckMate product (NetCheck)

2) Compass (formerly VTI) ... expensive?

3) A ftp-able cad system from Laboratoire MASI (France)
   which generates vhdl behavioral descriptions for a
   given netlist.  2 netlists -> 2 vhdl descriptions
   which can be compared (note, however, that in my case,
   the netlists contain a fair amount of analog circuitry).

4) VFormal (CAD Language Systems, Inc)

5) LVS (layout vs. schematic) checkers...

The most popular response steered me in the direction of
Carl Ebeling, CS professor at the University of Washington
(in my own backyard).  I'm guessing that GEMINI fits into
category (5)  (see above).  I've sent him e-mail, but so
far, no response.

I am new to CAD, so excuse my stupidity.  We have obtained
some 'flattened' netlists from my advisor's colleagues in
industry (and that is our starting point).  If we are
lucky enough to have a schematic, it's a hard-copy of a
drawing!  There is no 'layout' or 'schematic' data...
just the aforementioned netlist and the netlist which is the
output of the translator.

My 'newness' to CAD has also prevented me from understanding
some of the responses.  Excuse me if I'm violating 'netiquette'
by quoting from an e-mail response...

 'You can run a Layout-vs-schematic (LVS) check of the
  original layout vs. the new netlist.  We have Cadence Dracula.
  This will flatten both the layout and the schematic and do
  a topological comparison.'

a) as I've mentioned above, I don't have an 'original layout'.

b) (This is the part that confuses me, and is not related to
    my original question!) For *typical* LVS use, isn't the
    layout data generated by a circuit schematic and a set of
    design rules?  So why *wouldn't* the layout data *match*
    the schematic?

I'm so confused (but learning in leaps and bounds)!

Thanks for your help everybody,

Ivan Wemple