🚀 go-pugleaf

          PC dos version: 5.0 wuarchive.wustl.edu in
                          /mirrors/msdos/electrical/,
                          pspice5a.zip, pspice5b.zip, pspice5c.zip

          PC windows3 version 5.1: WSMR-SIMTEL20.Army.Mil in
                          pd1:<msdos.windows3>
                          called PSPIC51A.ZIP and PSPIC51B.ZIP

          Mac version 5.1: wuarchive.wustl.edu in
                          /mirrors/info-mac/app/pspice-51.hqx

  The PC version is also available at a number of U.S. and non-U.S. sites.

30: Esim:

  A new version of the switch-level simulator ESIM that can handle CMOS
  transmission gates is available through MUG, ftp venera.isi.edu
  (128.9.0.32))

31: Isplice3 (Current version 2.0):

  This is a high level simulator, I do not know much more then that.  It is
  available via anonymous ftp from uicadb.csl.uiuc.edu.

32: Watand:

  (From Phil Munro's posting <FC138001@ysub.ysu.edu>)

  Spice is not the only circuit simulator available.  There is one called
  WATAND (WATerloo ANalysis and Design) which runs on a mainframe (and some
  other workstations).  We use it here under CMS on our mainframe computer.

  Unlike Spice and its derivatives, Watand is a fully *interactive* pro-
  gram; that is, one enters an environment where analyses can be run and
  rerun, values changed and queried, options changed, and even different
  circuits can be run, all without leaving the environment.

     "WATAND Users Manual", by Dr. Phil Munro, April 1992, 233 pages,
     unbound, $7.00 plus whatever shipping charges the bookstore might ask
     of you.

     "WATAND Introduction and Examples", by Dr. P. Munro, September 1991,
     160 pages, spiral bound, incomplete edition Chapters 1 - 10.  The cost
     is $4 or $5, I think, plus shipping.

               You should write to Youngstown State University Bookstore
                               Youngstown, Ohio 44555

  Watand itself is available from Mark O'Leavey, Waterloo Engineering
  Software, 22 King St. S., Suite 302, Waterloo, Ontario, CANADA, N2L 1C6.
  Fax: (519) 746-7931 Phone: (519) 741-8097. It's currently only available
  for DECStation and Sparcstation.

33: Caltech VLSI CAD Tools:

  (From John Lazzaro <lazzaro@boom.CS.Berkeley.EDU>)

                     Caltech VLSI CAD Tool Distribution

  We are offering to the Internet community a pre-release version of the
  Caltech electronic CAD system for analog VLSI neural networks.  This dis-
  tribution contains tools for schematic capture, netlist creation, and
  analog and digital simulation (log), IC mask layout, extraction, and DRC
  (wol), simple chip compilation (wolcomp), MOSIS fabrication request gen-
  eration (mosis), netlist comparison (netcmp), data plotting (view) and
  postscript graphics editing (until). These tools were used exclusively
  for the design and test of all the integrated circuits described in
  Carver Mead's book "Analog VLSI and Neural Systems".  Until was used as
  the primary tool for figure creation for the book.  The distribution also
  contains an example of an analog VLSI chip that was designed and fabri-
  cated with these tools, and an example of an Actel field-programmable
  gate array design that was simulated and converted to Actel format with
  these tools.

  These tools are distributed under a license very similar to the GNU
  license; the minor changes protect Caltech from liability.

  To use these tools, you need:

  1) A unix workstation that runs X11r3, X11r4, or Openwindows

  2) A color screen

  3) Gcc or other ANSI-standard compiler

  Right now only Sun Sparcstations are officially supported, although
  resourceful users have the tools running on Sun 3, HP Series 300, and
  Decstations.  If don't have a Sparcstation or an HP 300, only take the
  package if you feel confident in your C/Unix abilities to do the porting
  required; someday soon we will integrate the changes back into the
  sources officially, although many "ifdef mips" are already in the code.

  If you are interested in some or all of these tools,

  1) ftp to hobiecat.cs.caltech.edu on the Internet,

  2) log in as anonymous and use your username as the password

  3) cd ~ftp/pub/chipmunk


  4) copy the file README, that contains more information.

  European researchers can access these files through anonymous ftp using
  the machine ifi.uio.no in Norway; the files are in the directory chip-
  munk.  We are unable to help users who do not have Internet ftp access.

34: Switcap2 (Current version 1.1):

  This is a switched capactor simulator.  It is available from:

                  SWITCAP Distribution centre,
                  411 Low Memorial Library,
                  New York,
                  N.Y. 10027.

35: Test Software for Abramovici Text:

  (Contributed by Mel Breuer of the Univ. of Southern California)

  Many faculty are using the text by Abramovici, Breuer, and Fried- man
  entitled  "Digital Systems Testing and Testable Design" in a class on
  testing.  They have expressed an interest to  supplement their  course
  with software tools.  At USC we have developed such a suite of tools.
  They include a  good  value  simulator,  fault simulator,  fault  col-
  lapsing  module, and D-algorithm-based ATPG module for combinational
  logic.  The software has  been  specifi- cally  designed  to  be easily
  understood, modified and enhanced.  The algorithms follow those described
  in the text.  The  software can  be  run  in many modes, such as one
  module at a time, single step, interactively or as a batch process.  Stu-
  dents can use  the software  "as  is"  to  study  the operation of the
  various algo- rithms, e.g. simulation of a latch using different delay
  models.  Also,  simple  programming  projects can be given, such as
  extend the simulator from a 3-valued system to  a  5-valued  system;  or
  change  the D-algorithm so that it only does single path sensiti- zation.
  There  are  literally  over  50  interesting   software enhancements
  that  can  be made by changing only a small part of the code.  The system
  is written in C and runs on a SUN.

  If you are currently using the Abramovici text and would  like  a copy
  of  this  software,  please  send a message to Prof. Melvin Breuer at
  mb@poisson.usc.edu.

36: Test Generation and Fault Simulation Software

  (Contributed by Dr. Dong Ha of Virginia Tech)

  Two automatic test pattern generators (ATPGs) and a fault simula- tor
  for  combinational circuits were developed at Virginia Tech, and the
  source codes of  the  tools  are  now  ready  for  public release.
  ATLANTA is an ATPG for stuck-at faults.  It is based on the FAN algorithm
  and a parallel-pattern,  single-fault  propaga- tion  technique.   It
  consists of optional sessions using random pattern testing, deterministic
  test pattern generation  and  test compaction.  SOPRANO is an ATPG for
  stuck-open faults.  The algo- rithm of SOPRANO is similar to  ATLANTA
  except  two  consecutive patterns  are  applied  to  detect a stuck-open
  fault.  FSIM is a parallel-pattern, single-fault  simulator.   All  the
  tools  are written  in  C.  The source codes are fully commented, and
  README files contain user's manuals.  Technical papers about  the  tools
  were  presented at DAC-90 and ITC-91. All three tools are free to univer-
  sities.  Companies are requested to make a contribution  of $5000  but
  will have free technical assistance.  For detailed in- formation, con-
  tact:

             Dr. Dong Ha
             Electrical Engineering
             Virginia Tech
             Blacksburg, VA 24061
             TEL: 703-231-4942
             FAX: 703-231-3362
             dsha@vtvm1.cc.vt.edu

37: Olympus Synthesis System

  (From Rajesh K. Gupta <rgupta@sirius.Stanford.EDU>)

  Recently there have been several enquiries about the Olympus Synthesis
  System. Here are answers to some commonly asked questions. For details
  please send mail to "synthesis@chronos.stanford.edu".

  1. What is Olympus Synthesis System?

  Olympus is a result of a continuing project on synthesis of digital cir-
  cuits here at Stanford University. Currently, Olympus synthesis system
  consists of a set of programs that perform synthesis tasks for synchro-
  nous, non-pipelined circuits starting from a description in a hardware
  description language, HardwareC.

  The output of synthesis is a technology independent netlist of gates.
  This netlist can be input to logic synthesis and technology mapping tools
  within Olympus or to UC Berkeley's mis/sis. Current technology mapping in
  Olympus is targeted for LSI logic standard cells and a set of PGA archi-
  tectures: Actel and Xilinx.

  2. How is Olympus distributed?

  The source code and documentation for Olympus is distributed via ftp.

  3. What are the system requirements for Olympus?

  Olympus has been tested on following hardware platforms: mips, sparc,
  hp9000s300, hp9000s800, hp9000s700, vax.  All the programs in Olympus
  come with a default menu-driven ASCII interface. There is also a graphi-
  cal user interface, called "olympus", provided with the distribution.
  This interface is written using Motif procedures.

  You would need about 40 MBytes of disk space to extract and compile the
  system.

  4. How can I obtain a copy of Olympus?

  Olympus is distributed free of charge by Stanford University.  However,
  it is not available via anonymous ftp. In order to obtain a copy please
  send a mail to "olympus@chronos.stanford.edu" where an automatic-reply
  mailer would send instructions for obtaining Olympus software.

38: OASIS logic synthesis

  (From William R. Richards Jr. <richards@mcnc.org>)

  OASIS is a complete logic synthesis system based on the Logic3 HDL
  develped at MCNC (unfortunately neither VHDL or Verilog compatible).
  kk@mcnc.org is the person responsible for it. OASIS is available to US
  universities for $500 and non-US universities for $600. Industrial
  license is $3000.

39: CAzM, a Spice-like table-based analog circuit simulator

  (From William R. Richards Jr. <richards@mcnc.org>)

  Second is CAzM, a Spice-like table-based analog circuit simulator. It
  offers significant performance advantages over other Berkeley Spice
  derivatives. It is used fairly extensively in our design community.  US
  university license is $175, non-US $250. Commercial license is $800. It
  comes with an X11- based signal viewing tool Sigview which is public
  domain and may be anonymous ftp'd from mcnc.org. I am the primary contact
  for CAzM at MCNC.

40: Galaxy CAD, integrated environment for digital design for Macintosh

  Thanks to Simon Leung <sleung@sun1.atitech.ca>

  The Galaxy CAD System is an integrated environment for digital design and
  for rapid prototyping of CAD tools and other software.  The system
  currently includes schematic capture and simulation of both low-level and
  high-level digital designs and is being expanded to include physical
  design tools.  Galaxy runs on a number of 680X0 platforms, including the
  Apple Macintosh, HP9000/3XX, Apollo Domain, and Atari ST.  Others will be
  added according to demand.

  The Galaxy CAD System is an ideal environment for teaching digital
  design.  It has been used successfully for both introductory logic design
  and computer design courses at Wisconsin.  Some of the features of Galaxy
  that make it suitable for education are:

  1.  Integrated multiple-window environment: All Galaxy tools run
      concurrently in a multiple window environment.  Copying data
      from one window to another is simple.  Any number of simulation
      sessions can be active simultaneously.

  2.  Hierarchy: the schematic editor and simulator are both fully
      hierarchical.  Building hierarchical designs is simple, including
      creating symbols for modules.  The simulator is a true hierarchical
      simulator: it does not require a time-consuming macro-expansion
      step.

  3.  Integrated editing and simulation: Designs are edited and
      simulated in the same environment.  Simulation input and output
      can be shown directly on schematics, allowing direct manipulation
      of net values.  Unlike other products, Galaxy does not require
      modification of the schematic to insert "switch" and "light"
      components.  In addition, Galaxy allows display of bus values in
      hexadecimal directly on schematics to simplify debugging of
      high-level designs.  Simulation I/O can also use waveforms,
      text files, and tables.

  4.  Faults: Stuck-at faults can be introduced on the schematic
      editor and simulated immediately without rebuilding the
      simulation model.  This provides an excellent way to display
      the effects of faults.

  5.  Buses: Galaxy supports specification and simulation of bus
      structures, including complex extractions, fanouts, and bit
      reversal.  Buses are specified by annotating nets with text.
      For simulation, buses are kept intact so that multiple-bit
      high-level components can be used.  Galaxy includes a library
      of register-transfer components suitable for high-level
      computer design and simulation.

  6.  Alternate specification of designs: In addition to schematics,
      Galaxy users can specify design modules using a textual HDL
      (GHDL) and using hardware flowcharts and state diagrams.  A
      hierarchical design can mix these representations as desired.

  7.  High-quality PostScript output: Galaxy schematics are of excellent
      quality.  Gates are drawn according to standard practices, e.g.,
      OR gates are drawn with the correct circular arcs and not ellipses.

  8.  Uniform user interface: Galaxy tools have the same user interface
      on all platforms, reducing student learning curves.  In fact,
      the same tool OBJECT CODE runs on all platforms due to the unique
      structure of Galaxy.

  9.  Adding new simulation primitives is straightforward.

  10. No cost: Galaxy is available for free via anonymous FTP (Apple
      Macintosh version).  Other versions will be made available based
      on demand.

  Galaxy is also an excellent environment for rapid prototyping of new CAD
  tools.  By building on top of available resources, we have been able to
  prototype new tools in days or weeks that would ordinarily have taken
  months or years.  For more information, send e-mail.

  To obtain Galaxy CAD, connect to "eceserv0.ece.wisc.edu" using FTP.  Log
  in as "anonymous" with password "guest".  Galaxy is in directory
  "pub/galaxy".  The file "README" in that directory gives further instruc-
  tions.  Please register as a user by sending e-mail to
  "beetem@engr.wisc.edu".

  John F. Beetem
  ECE Department
  University of Wisconsin - Madison
  Madison, WI  53706
  USA
  (608) 262-6229
  beetem@engr.wisc.edu

41: Gabriel DSP development system

  The Gabriel software is available via ftp from copernicus.Berkeley.EDU
  (128.32.240.37).  It's not quite "anonymous": you can use anonymous ftp
  to get the license agreement.  When you sign that and mail it back to us,
  we give you the password to an ftp account that allows you to grab the
  actual software.  It's free, just not anonymous.  :-)

  For the uninitiated, Gabriel is a block diagram programming environment
  for DSP that runs on Sun 3 and Sun 4 workstations.  It can simulate DSP
  designs, generate assembly code for Motorola DSP56000 and DSP96000 chips,
  and automatically perform parallel scheduling when multiple DSP chips are
  used.

  For more information, ftp to copernicus.Berkeley.EDU, log in as
  "anonymous" (any password will do), and grab the files "gabriel-
  overview", "gabriel-release-info", and "gabriel-license.shar".  Be warned
  that a new version of Gabriel will be out by the end of January, so if
  you're interested in it, it might pay to wait until then.

  Phil Lapsley
  phil@ucbarpa.Berkeley.EDU

42: WireC graphical/procedural system for schematic information

  (From Larry McMurchie <larry@cs.washington.edu>)

  WireC is a graphical specification language that combines schematics with
  procedural constructs for describing complex microelectronic systems.
  WireC allows the designer to choose the appropriate representation,
  either graphical or procedural, at a fine-grain level depending on the
  characteristics of the circuit being designed.  Drawing traditional
  schematic symbols and their interconnections provides fast intuitive
  interaction with a circuit design while procedural constructs give the
  power and flexibility to describe circuit structures algorithmically and
  allow single descriptions to represent whole families of devices.

  The procedural capability of WireC allows other CAD tools to be incor-
  porated into the design system.  For example, we have defined an inter-
  face to the SIS logic synthesis system wherein the designer can represent
  part of the system behaviorally.  WireC invokes logic synthesis on these
  components to produce a structural description that can be incorporated
  into the rest of the design.

  Libraries of devices defining a particular netlist output format may be
  defined by the user. The libraries currently distributed with WireC
  include a default CMOS gate library whose output is the SIM format.  This
  format can be simulated with COSMOS or IRSIM and compared against a cir-
  cuit extracted from layout.  This library also includes devices that
  allow a behavioral description to be synthesized and mapped using MIS or
  SIS and incorporated into a larger circuit.

  Another library is the xnf library for designing systems with Xilinx
  FPGAs.  Written by Jackson Kong, Martine Schlag and Pak Chan of UCSC,
  this library contains devices specific to the 2000 and 3000 series Xilinx
  LCA's.  In addition to drawing the devices explicitly, one can represent
  parts of a circuit with equations and have these synthesized automati-
  cally.

  Currently in progress is a library of CMOS gates for Cascade Design
  Automation's ChipCrafter product.  WireC provides a mixed
  schematic/procedural design frontend for ChipCrafter, which uses module
  generation, timing analysis and place and route software to create a phy-
  sical layout from the WireC design specification.

  WireC was written by Larry McMurchie, Carl Ebeling, Zhanbing Wu and Ed
  Tellman.  We are interested in any libraries you may develop and will
  provide a limited degree of support.

  WireC requires an X-Windows compatible environment and a C++ compiler
  such as Gnu G++ and AT&T CC.  WireC is available via ftp on the Internet.
  For details send mail to

  larry@cs.washington.edu ebeling@cs.washington.edu

43: LateX circuit symbols for schematic generation

  (From Adrian Johnstone <adrian@cs.rhbnc.ac.uk)

  A set of circuit schematic symbols are available for use in LaTeX picture
  mode. The set includes all basic logic gates in four orientations, FETs,
  power supply pins, transmission gates, capacitors, resistors and wiring
  T-junctions. All pins are on a 1mm grid and the symbols are designed to
  be easily used with Georg Horn's TeXcad program: we even supply you with
  a palette picture file that displays all 52 symbols in a compact grid
  that you can cut and paste from within TeXcad. Each symbol lives in its
  own .mac file and is defined as a 'savebox' so as to reduce memory con-
  sumption. You must add the [bezier] option to your 'documentstyle' com-
  mand. A small manual is provided in both Postscript and .dvi forms.

  The files lcircuit.zip and lcircuit.tar are available for anonymous ftp
  from cscx.cs.rhbnc.ac.uk (134.219.200.45) in directory pub/lcircuit. I
  will also be uploading them to various ftp servers in the coming week.

44: Tanner Research Tools (Ledit and LVS)

  (From Bhusan Gupta <bgupta@micro.caltech.edu>)

  There is a "low" cost tool from Tanner Research (Pasadena, Ca) called LVS
  that will compare two spice decks.  It is a tool that is still evolving
  and is flexible. It can be a lifesaver if you have to compare spice
  decks. It is much easier to use than netcmp/netcomp (the caltech VLSI
  tools). I realize that this is a commercial tool for $, but the only rea-
  son I suggest it is that it isn't as expensive as a tool from a main-line
  CAD vendor.  (University pricing is around $245 for the PC version, and
  $995 for the commercial version.)

  Tanner also sells a layout mask editor called Ledit which they sell for
  the PC, Sun, HP, and Mac platforms. It has a DRC tool, extract to spice,
  a cross-section viewer, etc for additional money.  The cross-section
  viewer is neat gadget in that given some of your design, it will show
  what the vertical cross-section looks like.  Demo versions are available.

  For more info contact Tanner Research - 180 N. Vinedo Ave. Pasadena 91107
  (818) 792-3000 or fax (818) 792-0300.